Lines Matching refs:qphy
850 int (*configure_dp_phy)(struct qmp_phy *qphy);
851 void (*configure_dp_tx)(struct qmp_phy *qphy);
852 int (*calibrate_dp_phy)(struct qmp_phy *qphy);
853 void (*dp_aux_init)(struct qmp_phy *qphy);
929 struct qmp_phy *qphy; member
966 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
967 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
968 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
969 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
971 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
972 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
973 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
974 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
976 static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy);
1419 static int qmp_combo_serdes_init(struct qmp_phy *qphy) in qmp_combo_serdes_init() argument
1421 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_serdes_init()
1422 void __iomem *serdes = qphy->serdes; in qmp_combo_serdes_init()
1423 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qmp_combo_serdes_init()
1460 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) in qcom_qmp_v3_phy_dp_aux_init() argument
1464 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1469 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); in qcom_qmp_v3_phy_dp_aux_init()
1471 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1477 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1483 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); in qcom_qmp_v3_phy_dp_aux_init()
1485 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v3_phy_dp_aux_init()
1486 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_phy_dp_aux_init()
1487 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v3_phy_dp_aux_init()
1488 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); in qcom_qmp_v3_phy_dp_aux_init()
1489 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); in qcom_qmp_v3_phy_dp_aux_init()
1490 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); in qcom_qmp_v3_phy_dp_aux_init()
1491 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); in qcom_qmp_v3_phy_dp_aux_init()
1492 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); in qcom_qmp_v3_phy_dp_aux_init()
1493 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); in qcom_qmp_v3_phy_dp_aux_init()
1494 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); in qcom_qmp_v3_phy_dp_aux_init()
1495 qphy->dp_aux_cfg = 0; in qcom_qmp_v3_phy_dp_aux_init()
1500 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); in qcom_qmp_v3_phy_dp_aux_init()
1503 static int qmp_combo_configure_dp_swing(struct qmp_phy *qphy, in qmp_combo_configure_dp_swing() argument
1506 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qmp_combo_configure_dp_swing()
1507 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_configure_dp_swing()
1533 writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); in qmp_combo_configure_dp_swing()
1534 writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); in qmp_combo_configure_dp_swing()
1535 writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); in qmp_combo_configure_dp_swing()
1536 writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); in qmp_combo_configure_dp_swing()
1541 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) in qcom_qmp_v3_phy_configure_dp_tx() argument
1543 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v3_phy_configure_dp_tx()
1546 if (qmp_combo_configure_dp_swing(qphy, QSERDES_V3_TX_TX_DRV_LVL, in qcom_qmp_v3_phy_configure_dp_tx()
1558 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); in qcom_qmp_v3_phy_configure_dp_tx()
1559 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v3_phy_configure_dp_tx()
1560 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); in qcom_qmp_v3_phy_configure_dp_tx()
1561 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v3_phy_configure_dp_tx()
1564 static bool qmp_combo_configure_dp_mode(struct qmp_phy *qphy) in qmp_combo_configure_dp_mode() argument
1587 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qmp_combo_configure_dp_mode()
1589 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); in qmp_combo_configure_dp_mode()
1594 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) in qcom_qmp_v3_phy_configure_dp_phy() argument
1596 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; in qcom_qmp_v3_phy_configure_dp_phy()
1597 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v3_phy_configure_dp_phy()
1601 qmp_combo_configure_dp_mode(qphy); in qcom_qmp_v3_phy_configure_dp_phy()
1603 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); in qcom_qmp_v3_phy_configure_dp_phy()
1604 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); in qcom_qmp_v3_phy_configure_dp_phy()
1627 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); in qcom_qmp_v3_phy_configure_dp_phy()
1632 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v3_phy_configure_dp_phy()
1633 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1634 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1635 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1636 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1638 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); in qcom_qmp_v3_phy_configure_dp_phy()
1640 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
1647 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1649 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
1656 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1658 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
1660 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
1671 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) in qcom_qmp_v3_dp_phy_calibrate() argument
1676 qphy->dp_aux_cfg++; in qcom_qmp_v3_dp_phy_calibrate()
1677 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); in qcom_qmp_v3_dp_phy_calibrate()
1678 val = cfg1_settings[qphy->dp_aux_cfg]; in qcom_qmp_v3_dp_phy_calibrate()
1680 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_dp_phy_calibrate()
1685 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) in qcom_qmp_v4_phy_dp_aux_init() argument
1689 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v4_phy_dp_aux_init()
1692 writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_qmp_v4_phy_dp_aux_init()
1694 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v4_phy_dp_aux_init()
1695 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v4_phy_dp_aux_init()
1696 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v4_phy_dp_aux_init()
1697 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); in qcom_qmp_v4_phy_dp_aux_init()
1698 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); in qcom_qmp_v4_phy_dp_aux_init()
1699 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); in qcom_qmp_v4_phy_dp_aux_init()
1700 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); in qcom_qmp_v4_phy_dp_aux_init()
1701 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); in qcom_qmp_v4_phy_dp_aux_init()
1702 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); in qcom_qmp_v4_phy_dp_aux_init()
1703 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); in qcom_qmp_v4_phy_dp_aux_init()
1704 qphy->dp_aux_cfg = 0; in qcom_qmp_v4_phy_dp_aux_init()
1709 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); in qcom_qmp_v4_phy_dp_aux_init()
1712 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) in qcom_qmp_v4_phy_configure_dp_tx() argument
1715 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); in qcom_qmp_v4_phy_configure_dp_tx()
1716 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); in qcom_qmp_v4_phy_configure_dp_tx()
1718 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); in qcom_qmp_v4_phy_configure_dp_tx()
1719 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); in qcom_qmp_v4_phy_configure_dp_tx()
1721 qmp_combo_configure_dp_swing(qphy, QSERDES_V4_TX_TX_DRV_LVL, in qcom_qmp_v4_phy_configure_dp_tx()
1725 static int qcom_qmp_v45_phy_configure_dp_phy(struct qmp_phy *qphy) in qcom_qmp_v45_phy_configure_dp_phy() argument
1727 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; in qcom_qmp_v45_phy_configure_dp_phy()
1728 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v45_phy_configure_dp_phy()
1732 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); in qcom_qmp_v45_phy_configure_dp_phy()
1734 qmp_combo_configure_dp_mode(qphy); in qcom_qmp_v45_phy_configure_dp_phy()
1736 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v45_phy_configure_dp_phy()
1737 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v45_phy_configure_dp_phy()
1739 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); in qcom_qmp_v45_phy_configure_dp_phy()
1740 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); in qcom_qmp_v45_phy_configure_dp_phy()
1763 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); in qcom_qmp_v45_phy_configure_dp_phy()
1768 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1769 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1770 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1771 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1773 writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); in qcom_qmp_v45_phy_configure_dp_phy()
1775 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1782 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1789 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1796 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v45_phy_configure_dp_phy()
1798 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1805 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v45_phy_configure_dp_phy()
1815 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) in qcom_qmp_v4_phy_configure_dp_phy() argument
1817 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v4_phy_configure_dp_phy()
1823 ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); in qcom_qmp_v4_phy_configure_dp_phy()
1849 writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); in qcom_qmp_v4_phy_configure_dp_phy()
1850 writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v4_phy_configure_dp_phy()
1851 writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); in qcom_qmp_v4_phy_configure_dp_phy()
1852 writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v4_phy_configure_dp_phy()
1854 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
1856 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
1858 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v4_phy_configure_dp_phy()
1865 writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); in qcom_qmp_v4_phy_configure_dp_phy()
1866 writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); in qcom_qmp_v4_phy_configure_dp_phy()
1868 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); in qcom_qmp_v4_phy_configure_dp_phy()
1869 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); in qcom_qmp_v4_phy_configure_dp_phy()
1871 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); in qcom_qmp_v4_phy_configure_dp_phy()
1872 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); in qcom_qmp_v4_phy_configure_dp_phy()
1877 static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy) in qcom_qmp_v5_phy_configure_dp_phy() argument
1879 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; in qcom_qmp_v5_phy_configure_dp_phy()
1885 ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); in qcom_qmp_v5_phy_configure_dp_phy()
1906 writel(drvr0_en, qphy->tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); in qcom_qmp_v5_phy_configure_dp_phy()
1907 writel(bias0_en, qphy->tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v5_phy_configure_dp_phy()
1908 writel(drvr1_en, qphy->tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); in qcom_qmp_v5_phy_configure_dp_phy()
1909 writel(bias1_en, qphy->tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); in qcom_qmp_v5_phy_configure_dp_phy()
1911 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v5_phy_configure_dp_phy()
1913 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v5_phy_configure_dp_phy()
1915 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v5_phy_configure_dp_phy()
1922 writel(0x0a, qphy->tx + QSERDES_V5_5NM_TX_TX_POL_INV); in qcom_qmp_v5_phy_configure_dp_phy()
1923 writel(0x0a, qphy->tx2 + QSERDES_V5_5NM_TX_TX_POL_INV); in qcom_qmp_v5_phy_configure_dp_phy()
1925 writel(0x27, qphy->tx + QSERDES_V5_5NM_TX_TX_DRV_LVL); in qcom_qmp_v5_phy_configure_dp_phy()
1926 writel(0x27, qphy->tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL); in qcom_qmp_v5_phy_configure_dp_phy()
1928 writel(0x20, qphy->tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); in qcom_qmp_v5_phy_configure_dp_phy()
1929 writel(0x20, qphy->tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); in qcom_qmp_v5_phy_configure_dp_phy()
1938 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) in qcom_qmp_v4_dp_phy_calibrate() argument
1943 qphy->dp_aux_cfg++; in qcom_qmp_v4_dp_phy_calibrate()
1944 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); in qcom_qmp_v4_dp_phy_calibrate()
1945 val = cfg1_settings[qphy->dp_aux_cfg]; in qcom_qmp_v4_dp_phy_calibrate()
1947 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v4_dp_phy_calibrate()
1955 struct qmp_phy *qphy = phy_get_drvdata(phy); in qcom_qmp_dp_phy_configure() local
1956 const struct qmp_phy_cfg *cfg = qphy->cfg; in qcom_qmp_dp_phy_configure()
1958 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); in qcom_qmp_dp_phy_configure()
1959 if (qphy->dp_opts.set_voltages) { in qcom_qmp_dp_phy_configure()
1960 cfg->configure_dp_tx(qphy); in qcom_qmp_dp_phy_configure()
1961 qphy->dp_opts.set_voltages = 0; in qcom_qmp_dp_phy_configure()
1969 struct qmp_phy *qphy = phy_get_drvdata(phy); in qcom_qmp_dp_phy_calibrate() local
1970 const struct qmp_phy_cfg *cfg = qphy->cfg; in qcom_qmp_dp_phy_calibrate()
1973 return cfg->calibrate_dp_phy(qphy); in qcom_qmp_dp_phy_calibrate()
1978 static int qmp_combo_com_init(struct qmp_phy *qphy) in qmp_combo_com_init() argument
1980 struct qcom_qmp *qmp = qphy->qmp; in qmp_combo_com_init()
1981 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_com_init()
2057 static int qmp_combo_com_exit(struct qmp_phy *qphy) in qmp_combo_com_exit() argument
2059 struct qcom_qmp *qmp = qphy->qmp; in qmp_combo_com_exit()
2060 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_com_exit()
2083 struct qmp_phy *qphy = phy_get_drvdata(phy); in qmp_combo_init() local
2084 struct qcom_qmp *qmp = qphy->qmp; in qmp_combo_init()
2085 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_init()
2089 ret = qmp_combo_com_init(qphy); in qmp_combo_init()
2094 cfg->dp_aux_init(qphy); in qmp_combo_init()
2101 struct qmp_phy *qphy = phy_get_drvdata(phy); in qmp_combo_power_on() local
2102 struct qcom_qmp *qmp = qphy->qmp; in qmp_combo_power_on()
2103 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_power_on()
2104 void __iomem *tx = qphy->tx; in qmp_combo_power_on()
2105 void __iomem *rx = qphy->rx; in qmp_combo_power_on()
2106 void __iomem *pcs = qphy->pcs; in qmp_combo_power_on()
2111 qmp_combo_serdes_init(qphy); in qmp_combo_power_on()
2113 ret = clk_prepare_enable(qphy->pipe_clk); in qmp_combo_power_on()
2123 qmp_combo_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, in qmp_combo_power_on()
2129 cfg->configure_dp_tx(qphy); in qmp_combo_power_on()
2134 qmp_combo_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, in qmp_combo_power_on()
2140 cfg->configure_dp_phy(qphy); in qmp_combo_power_on()
2171 clk_disable_unprepare(qphy->pipe_clk); in qmp_combo_power_on()
2178 struct qmp_phy *qphy = phy_get_drvdata(phy); in qmp_combo_power_off() local
2179 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_power_off()
2181 clk_disable_unprepare(qphy->pipe_clk); in qmp_combo_power_off()
2185 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qmp_combo_power_off()
2188 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_power_off()
2191 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qmp_combo_power_off()
2195 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_combo_power_off()
2198 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, in qmp_combo_power_off()
2208 struct qmp_phy *qphy = phy_get_drvdata(phy); in qmp_combo_exit() local
2210 qmp_combo_com_exit(qphy); in qmp_combo_exit()
2242 struct qmp_phy *qphy = phy_get_drvdata(phy); in qmp_combo_set_mode() local
2244 qphy->mode = mode; in qmp_combo_set_mode()
2249 static void qmp_combo_enable_autonomous_mode(struct qmp_phy *qphy) in qmp_combo_enable_autonomous_mode() argument
2251 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_enable_autonomous_mode()
2252 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; in qmp_combo_enable_autonomous_mode()
2253 void __iomem *pcs_misc = qphy->pcs_misc; in qmp_combo_enable_autonomous_mode()
2256 if (qphy->mode == PHY_MODE_USB_HOST_SS || in qmp_combo_enable_autonomous_mode()
2257 qphy->mode == PHY_MODE_USB_DEVICE_SS) in qmp_combo_enable_autonomous_mode()
2278 static void qmp_combo_disable_autonomous_mode(struct qmp_phy *qphy) in qmp_combo_disable_autonomous_mode() argument
2280 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_disable_autonomous_mode()
2281 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; in qmp_combo_disable_autonomous_mode()
2282 void __iomem *pcs_misc = qphy->pcs_misc; in qmp_combo_disable_autonomous_mode()
2299 struct qmp_phy *qphy = qmp->phys[0]; in qmp_combo_runtime_suspend() local
2300 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_runtime_suspend()
2302 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); in qmp_combo_runtime_suspend()
2313 qmp_combo_enable_autonomous_mode(qphy); in qmp_combo_runtime_suspend()
2315 clk_disable_unprepare(qphy->pipe_clk); in qmp_combo_runtime_suspend()
2324 struct qmp_phy *qphy = qmp->phys[0]; in qmp_combo_runtime_resume() local
2325 const struct qmp_phy_cfg *cfg = qphy->cfg; in qmp_combo_runtime_resume()
2328 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); in qmp_combo_runtime_resume()
2343 ret = clk_prepare_enable(qphy->pipe_clk); in qmp_combo_runtime_resume()
2350 qmp_combo_disable_autonomous_mode(qphy); in qmp_combo_runtime_resume()
2550 const struct qmp_phy *qphy; in qcom_qmp_dp_pixel_clk_recalc_rate() local
2554 qphy = dp_clks->qphy; in qcom_qmp_dp_pixel_clk_recalc_rate()
2555 dp_opts = &qphy->dp_opts; in qcom_qmp_dp_pixel_clk_recalc_rate()
2594 const struct qmp_phy *qphy; in qcom_qmp_dp_link_clk_recalc_rate() local
2598 qphy = dp_clks->qphy; in qcom_qmp_dp_link_clk_recalc_rate()
2599 dp_opts = &qphy->dp_opts; in qcom_qmp_dp_link_clk_recalc_rate()
2634 static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, in phy_dp_clks_register() argument
2646 dp_clks->qphy = qphy; in phy_dp_clks_register()
2647 qphy->dp_clks = dp_clks; in phy_dp_clks_register()
2699 struct qmp_phy *qphy; in qmp_combo_create() local
2703 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); in qmp_combo_create()
2704 if (!qphy) in qmp_combo_create()
2707 qphy->cfg = cfg; in qmp_combo_create()
2708 qphy->serdes = serdes; in qmp_combo_create()
2715 qphy->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_combo_create()
2716 if (IS_ERR(qphy->tx)) in qmp_combo_create()
2717 return PTR_ERR(qphy->tx); in qmp_combo_create()
2719 qphy->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_combo_create()
2720 if (IS_ERR(qphy->rx)) in qmp_combo_create()
2721 return PTR_ERR(qphy->rx); in qmp_combo_create()
2723 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_combo_create()
2724 if (IS_ERR(qphy->pcs)) in qmp_combo_create()
2725 return PTR_ERR(qphy->pcs); in qmp_combo_create()
2728 qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; in qmp_combo_create()
2731 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_combo_create()
2732 if (IS_ERR(qphy->tx2)) in qmp_combo_create()
2733 return PTR_ERR(qphy->tx2); in qmp_combo_create()
2735 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_combo_create()
2736 if (IS_ERR(qphy->rx2)) in qmp_combo_create()
2737 return PTR_ERR(qphy->rx2); in qmp_combo_create()
2739 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_combo_create()
2741 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_combo_create()
2744 if (IS_ERR(qphy->pcs_misc)) { in qmp_combo_create()
2746 qphy->pcs_misc = NULL; in qmp_combo_create()
2756 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); in qmp_combo_create()
2757 if (IS_ERR(qphy->pipe_clk)) { in qmp_combo_create()
2759 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), in qmp_combo_create()
2762 qphy->pipe_clk = NULL; in qmp_combo_create()
2777 qphy->phy = generic_phy; in qmp_combo_create()
2778 qphy->qmp = qmp; in qmp_combo_create()
2779 qmp->phys[id] = qphy; in qmp_combo_create()
2780 phy_set_drvdata(generic_phy, qphy); in qmp_combo_create()