91 	void __iomem *tx1;  member
272 	writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);  in qcom_edp_set_voltages()
273 	writel(swing, edp->tx1 + TXn_TX_DRV_LVL);  in qcom_edp_set_voltages()
274 	writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_set_voltages()
476 	writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);  in qcom_edp_phy_power_on()
478 	writel(0x00, edp->tx1 + TXn_LANE_MODE_1);  in qcom_edp_phy_power_on()
502 	writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
503 	writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE);  in qcom_edp_phy_power_on()
504 	writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN);  in qcom_edp_phy_power_on()
505 	writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);  in qcom_edp_phy_power_on()
506 	writel(0x04, edp->tx1 + TXn_TX_BAND);  in qcom_edp_phy_power_on()
528 	writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
529 	writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
530 	writel(0x00, edp->tx1 + TXn_TX_POL_INV);  in qcom_edp_phy_power_on()
532 	writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET);  in qcom_edp_phy_power_on()
535 	writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0);  in qcom_edp_phy_power_on()
536 	writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1);  in qcom_edp_phy_power_on()
539 	writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_phy_power_on()
541 	writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL);  in qcom_edp_phy_power_on()
565 	writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
566 	writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
795 	edp->tx1 = devm_platform_ioremap_resource(pdev, 2);  in qcom_edp_phy_probe()
796 	if (IS_ERR(edp->tx1))  in qcom_edp_phy_probe()
797 		return PTR_ERR(edp->tx1);  in qcom_edp_phy_probe()