340 	struct mtk_phy_instance *instance)  in hs_slew_rate_calibrate()  argument
342 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in hs_slew_rate_calibrate()
354 	if (instance->eye_src)  in hs_slew_rate_calibrate()
369 		tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);  in hs_slew_rate_calibrate()
398 		instance->index, fm_out, calibration_val,  in hs_slew_rate_calibrate()
410 	struct mtk_phy_instance *instance)  in u3_phy_instance_init()  argument
412 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in u3_phy_instance_init()
438 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in u3_phy_instance_init()
442 	struct mtk_phy_instance *instance)  in u2_phy_pll_26m_set()  argument
444 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_pll_26m_set()
461 	struct mtk_phy_instance *instance)  in u2_phy_instance_init()  argument
463 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_init()
465 	u32 index = instance->index;  in u2_phy_instance_init()
501 	u2_phy_pll_26m_set(tphy, instance);  in u2_phy_instance_init()
507 	struct mtk_phy_instance *instance)  in u2_phy_instance_power_on()  argument
509 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_on()
511 	u32 index = instance->index;  in u2_phy_instance_power_on()
529 	struct mtk_phy_instance *instance)  in u2_phy_instance_power_off()  argument
531 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_off()
533 	u32 index = instance->index;  in u2_phy_instance_power_off()
552 	struct mtk_phy_instance *instance)  in u2_phy_instance_exit()  argument
554 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_exit()
556 	u32 index = instance->index;  in u2_phy_instance_exit()
566 				     struct mtk_phy_instance *instance,  in u2_phy_instance_set_mode()  argument
569 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_set_mode()
591 	struct mtk_phy_instance *instance)  in pcie_phy_instance_init()  argument
593 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in pcie_phy_instance_init()
637 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in pcie_phy_instance_init()
641 	struct mtk_phy_instance *instance)  in pcie_phy_instance_power_on()  argument
643 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_on()
653 	struct mtk_phy_instance *instance)  in pcie_phy_instance_power_off()  argument
656 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_off()
666 	struct mtk_phy_instance *instance)  in sata_phy_instance_init()  argument
668 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in sata_phy_instance_init()
707 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in sata_phy_instance_init()
711 			      struct mtk_phy_instance *instance)  in phy_v1_banks_init()  argument
713 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v1_banks_init()
714 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v1_banks_init()
716 	switch (instance->type) {  in phy_v1_banks_init()
720 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;  in phy_v1_banks_init()
726 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
727 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;  in phy_v1_banks_init()
730 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
739 			      struct mtk_phy_instance *instance)  in phy_v2_banks_init()  argument
741 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v2_banks_init()
742 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v2_banks_init()
744 	switch (instance->type) {  in phy_v2_banks_init()
746 		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;  in phy_v2_banks_init()
747 		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;  in phy_v2_banks_init()
748 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;  in phy_v2_banks_init()
752 		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;  in phy_v2_banks_init()
753 		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;  in phy_v2_banks_init()
754 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;  in phy_v2_banks_init()
755 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;  in phy_v2_banks_init()
764 				struct mtk_phy_instance *instance)  in phy_parse_property()  argument
766 	struct device *dev = &instance->phy->dev;  in phy_parse_property()
768 	if (instance->type != PHY_TYPE_USB2)  in phy_parse_property()
771 	instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");  in phy_parse_property()
773 				 &instance->eye_src);  in phy_parse_property()
775 				 &instance->eye_vrt);  in phy_parse_property()
777 				 &instance->eye_term);  in phy_parse_property()
779 				 &instance->intr);  in phy_parse_property()
781 				 &instance->discth);  in phy_parse_property()
783 				 &instance->pre_emphasis);  in phy_parse_property()
785 		instance->bc12_en, instance->eye_src,  in phy_parse_property()
786 		instance->eye_vrt, instance->eye_term,  in phy_parse_property()
787 		instance->intr, instance->discth);  in phy_parse_property()
788 	dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);  in phy_parse_property()
792 			     struct mtk_phy_instance *instance)  in u2_phy_props_set()  argument
794 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_props_set()
797 	if (instance->bc12_en) /* BC1.2 path Enable */  in u2_phy_props_set()
800 	if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)  in u2_phy_props_set()
802 				     instance->eye_src);  in u2_phy_props_set()
804 	if (instance->eye_vrt)  in u2_phy_props_set()
806 				     instance->eye_vrt);  in u2_phy_props_set()
808 	if (instance->eye_term)  in u2_phy_props_set()
810 				     instance->eye_term);  in u2_phy_props_set()
812 	if (instance->intr) {  in u2_phy_props_set()
818 				     instance->intr);  in u2_phy_props_set()
821 	if (instance->discth)  in u2_phy_props_set()
823 				     instance->discth);  in u2_phy_props_set()
825 	if (instance->pre_emphasis)  in u2_phy_props_set()
827 				     instance->pre_emphasis);  in u2_phy_props_set()
831 static int phy_type_syscon_get(struct mtk_phy_instance *instance,  in phy_type_syscon_get()  argument
846 	instance->type_sw_reg = args.args[0];  in phy_type_syscon_get()
847 	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */  in phy_type_syscon_get()
848 	instance->type_sw = syscon_node_to_regmap(args.np);  in phy_type_syscon_get()
850 	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",  in phy_type_syscon_get()
851 		 instance->type_sw_reg, instance->type_sw_index);  in phy_type_syscon_get()
853 	return PTR_ERR_OR_ZERO(instance->type_sw);  in phy_type_syscon_get()
856 static int phy_type_set(struct mtk_phy_instance *instance)  in phy_type_set()  argument
861 	if (!instance->type_sw)  in phy_type_set()
864 	switch (instance->type) {  in phy_type_set()
882 	offset = instance->type_sw_index * BITS_PER_BYTE;  in phy_type_set()
883 	regmap_update_bits(instance->type_sw, instance->type_sw_reg,  in phy_type_set()
889 static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance)  in phy_efuse_get()  argument
891 	struct device *dev = &instance->phy->dev;  in phy_efuse_get()
896 		instance->efuse_sw_en = 0;  in phy_efuse_get()
901 	instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells");  in phy_efuse_get()
902 	if (!instance->efuse_sw_en)  in phy_efuse_get()
905 	switch (instance->type) {  in phy_efuse_get()
907 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
914 		if (!instance->efuse_intr) {  in phy_efuse_get()
916 			instance->efuse_sw_en = 0;  in phy_efuse_get()
920 		dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);  in phy_efuse_get()
925 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
931 		ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);  in phy_efuse_get()
937 		ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);  in phy_efuse_get()
944 		if (!instance->efuse_intr &&  in phy_efuse_get()
945 		    !instance->efuse_rx_imp &&  in phy_efuse_get()
946 		    !instance->efuse_tx_imp) {  in phy_efuse_get()
948 			instance->efuse_sw_en = 0;  in phy_efuse_get()
953 			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);  in phy_efuse_get()
956 		dev_err(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_get()
963 static void phy_efuse_set(struct mtk_phy_instance *instance)  in phy_efuse_set()  argument
965 	struct device *dev = &instance->phy->dev;  in phy_efuse_set()
966 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_efuse_set()
967 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_efuse_set()
969 	if (!instance->efuse_sw_en)  in phy_efuse_set()
972 	switch (instance->type) {  in phy_efuse_set()
977 				     instance->efuse_intr);  in phy_efuse_set()
984 				    instance->efuse_tx_imp);  in phy_efuse_set()
988 				    instance->efuse_rx_imp);  in phy_efuse_set()
992 				    instance->efuse_intr);  in phy_efuse_set()
995 		dev_warn(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_set()
1002 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_init()  local
1006 	ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1010 	phy_efuse_set(instance);  in mtk_phy_init()
1012 	switch (instance->type) {  in mtk_phy_init()
1014 		u2_phy_instance_init(tphy, instance);  in mtk_phy_init()
1015 		u2_phy_props_set(tphy, instance);  in mtk_phy_init()
1018 		u3_phy_instance_init(tphy, instance);  in mtk_phy_init()
1021 		pcie_phy_instance_init(tphy, instance);  in mtk_phy_init()
1024 		sata_phy_instance_init(tphy, instance);  in mtk_phy_init()
1031 		clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1040 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_power_on()  local
1043 	if (instance->type == PHY_TYPE_USB2) {  in mtk_phy_power_on()
1044 		u2_phy_instance_power_on(tphy, instance);  in mtk_phy_power_on()
1045 		hs_slew_rate_calibrate(tphy, instance);  in mtk_phy_power_on()
1046 	} else if (instance->type == PHY_TYPE_PCIE) {  in mtk_phy_power_on()
1047 		pcie_phy_instance_power_on(tphy, instance);  in mtk_phy_power_on()
1055 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_power_off()  local
1058 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_power_off()
1059 		u2_phy_instance_power_off(tphy, instance);  in mtk_phy_power_off()
1060 	else if (instance->type == PHY_TYPE_PCIE)  in mtk_phy_power_off()
1061 		pcie_phy_instance_power_off(tphy, instance);  in mtk_phy_power_off()
1068 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_exit()  local
1071 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_exit()
1072 		u2_phy_instance_exit(tphy, instance);  in mtk_phy_exit()
1074 	clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_exit()
1080 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_set_mode()  local
1083 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_set_mode()
1084 		u2_phy_instance_set_mode(tphy, instance, mode);  in mtk_phy_set_mode()
1093 	struct mtk_phy_instance *instance = NULL;  in mtk_phy_xlate()  local
1105 			instance = tphy->phys[index];  in mtk_phy_xlate()
1109 	if (!instance) {  in mtk_phy_xlate()
1114 	instance->type = args->args[0];  in mtk_phy_xlate()
1115 	if (!(instance->type == PHY_TYPE_USB2 ||  in mtk_phy_xlate()
1116 	      instance->type == PHY_TYPE_USB3 ||  in mtk_phy_xlate()
1117 	      instance->type == PHY_TYPE_PCIE ||  in mtk_phy_xlate()
1118 	      instance->type == PHY_TYPE_SATA ||  in mtk_phy_xlate()
1119 	      instance->type == PHY_TYPE_SGMII)) {  in mtk_phy_xlate()
1120 		dev_err(dev, "unsupported device type: %d\n", instance->type);  in mtk_phy_xlate()
1126 		phy_v1_banks_init(tphy, instance);  in mtk_phy_xlate()
1130 		phy_v2_banks_init(tphy, instance);  in mtk_phy_xlate()
1137 	ret = phy_efuse_get(tphy, instance);  in mtk_phy_xlate()
1141 	phy_parse_property(tphy, instance);  in mtk_phy_xlate()
1142 	phy_type_set(instance);  in mtk_phy_xlate()
1144 	return instance->phy;  in mtk_phy_xlate()
1246 		struct mtk_phy_instance *instance;  in mtk_tphy_probe()  local
1251 		instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);  in mtk_tphy_probe()
1252 		if (!instance) {  in mtk_tphy_probe()
1257 		tphy->phys[port] = instance;  in mtk_tphy_probe()
1274 		instance->port_base = devm_ioremap_resource(subdev, &res);  in mtk_tphy_probe()
1275 		if (IS_ERR(instance->port_base)) {  in mtk_tphy_probe()
1276 			retval = PTR_ERR(instance->port_base);  in mtk_tphy_probe()
1280 		instance->phy = phy;  in mtk_tphy_probe()
1281 		instance->index = port;  in mtk_tphy_probe()
1282 		phy_set_drvdata(phy, instance);  in mtk_tphy_probe()
1285 		clks = instance->clks;  in mtk_tphy_probe()
1292 		retval = phy_type_syscon_get(instance, child_np);  in mtk_tphy_probe()