Lines Matching refs:pci_dbg
1355 pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1532 pci_dbg(bridge, "re-enabling LTR\n");
1654 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1686 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
2520 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
4387 pci_dbg(dev, "%s bus mastering\n",
4488 pci_dbg(dev, "cache line size of %d is not supported\n",
4517 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
5001 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
5027 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5030 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5040 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);