169 static void start_int_poll_timer(struct controller *ctrl, int sec);
170 static int hpc_check_cmd_status(struct controller *ctrl);
172 static inline u8 shpc_readb(struct controller *ctrl, int reg)  in shpc_readb()  argument
174 	return readb(ctrl->creg + reg);  in shpc_readb()
177 static inline u16 shpc_readw(struct controller *ctrl, int reg)  in shpc_readw()  argument
179 	return readw(ctrl->creg + reg);  in shpc_readw()
182 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)  in shpc_writew()  argument
184 	writew(val, ctrl->creg + reg);  in shpc_writew()
187 static inline u32 shpc_readl(struct controller *ctrl, int reg)  in shpc_readl()  argument
189 	return readl(ctrl->creg + reg);  in shpc_readl()
192 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)  in shpc_writel()  argument
194 	writel(val, ctrl->creg + reg);  in shpc_writel()
197 static inline int shpc_indirect_read(struct controller *ctrl, int index,  in shpc_indirect_read()  argument
201 	u32 cap_offset = ctrl->cap_offset;  in shpc_indirect_read()
202 	struct pci_dev *pdev = ctrl->pci_dev;  in shpc_indirect_read()
215 	struct controller *ctrl = from_timer(ctrl, t, poll_timer);  in int_poll_timeout()  local
218 	shpc_isr(0, ctrl);  in int_poll_timeout()
223 	start_int_poll_timer(ctrl, shpchp_poll_time);  in int_poll_timeout()
229 static void start_int_poll_timer(struct controller *ctrl, int sec)  in start_int_poll_timer()  argument
235 	ctrl->poll_timer.expires = jiffies + sec * HZ;  in start_int_poll_timer()
236 	add_timer(&ctrl->poll_timer);  in start_int_poll_timer()
239 static inline int is_ctrl_busy(struct controller *ctrl)  in is_ctrl_busy()  argument
241 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);  in is_ctrl_busy()
249 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)  in shpc_poll_ctrl_busy()  argument
253 	if (!is_ctrl_busy(ctrl))  in shpc_poll_ctrl_busy()
259 		if (!is_ctrl_busy(ctrl))  in shpc_poll_ctrl_busy()
266 static inline int shpc_wait_cmd(struct controller *ctrl)  in shpc_wait_cmd()  argument
273 		rc = shpc_poll_ctrl_busy(ctrl);  in shpc_wait_cmd()
275 		rc = wait_event_interruptible_timeout(ctrl->queue,  in shpc_wait_cmd()
276 						!is_ctrl_busy(ctrl), timeout);  in shpc_wait_cmd()
277 	if (!rc && is_ctrl_busy(ctrl)) {  in shpc_wait_cmd()
279 		ctrl_err(ctrl, "Command not completed in 1000 msec\n");  in shpc_wait_cmd()
282 		ctrl_info(ctrl, "Command was interrupted by a signal\n");  in shpc_wait_cmd()
290 	struct controller *ctrl = slot->ctrl;  in shpc_write_cmd()  local
295 	mutex_lock(&slot->ctrl->cmd_lock);  in shpc_write_cmd()
297 	if (!shpc_poll_ctrl_busy(ctrl)) {  in shpc_write_cmd()
299 		ctrl_err(ctrl, "Controller is still busy after 1 sec\n");  in shpc_write_cmd()
306 	ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);  in shpc_write_cmd()
311 	shpc_writew(ctrl, CMD, temp_word);  in shpc_write_cmd()
316 	retval = shpc_wait_cmd(slot->ctrl);  in shpc_write_cmd()
320 	cmd_status = hpc_check_cmd_status(slot->ctrl);  in shpc_write_cmd()
322 		ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",  in shpc_write_cmd()
327 	mutex_unlock(&slot->ctrl->cmd_lock);  in shpc_write_cmd()
331 static int hpc_check_cmd_status(struct controller *ctrl)  in hpc_check_cmd_status()  argument
334 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;  in hpc_check_cmd_status()
342 		ctrl_err(ctrl, "Switch opened!\n");  in hpc_check_cmd_status()
346 		ctrl_err(ctrl, "Invalid HPC command!\n");  in hpc_check_cmd_status()
350 		ctrl_err(ctrl, "Invalid bus speed/mode!\n");  in hpc_check_cmd_status()
362 	struct controller *ctrl = slot->ctrl;  in hpc_get_attention_status()  local
363 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_attention_status()
386 	struct controller *ctrl = slot->ctrl;  in hpc_get_power_status()  local
387 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_power_status()
411 	struct controller *ctrl = slot->ctrl;  in hpc_get_latch_status()  local
412 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_latch_status()
421 	struct controller *ctrl = slot->ctrl;  in hpc_get_adapter_status()  local
422 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_adapter_status()
432 	struct controller *ctrl = slot->ctrl;  in hpc_get_prog_int()  local
434 	*prog_int = shpc_readb(ctrl, PROG_INTERFACE);  in hpc_get_prog_int()
442 	struct controller *ctrl = slot->ctrl;  in hpc_get_adapter_speed()  local
443 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_adapter_speed()
462 	ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",  in hpc_get_adapter_speed()
488 	ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);  in hpc_get_adapter_speed()
495 	struct controller *ctrl = slot->ctrl;  in hpc_get_mode1_ECC_cap()  local
496 	u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);  in hpc_get_mode1_ECC_cap()
497 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in hpc_get_mode1_ECC_cap()
505 	ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);  in hpc_get_mode1_ECC_cap()
511 	struct controller *ctrl = slot->ctrl;  in hpc_query_power_fault()  local
512 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_query_power_fault()
555 static void hpc_release_ctlr(struct controller *ctrl)  in hpc_release_ctlr()  argument
563 	for (i = 0; i < ctrl->num_slots; i++) {  in hpc_release_ctlr()
564 		slot_reg = shpc_readl(ctrl, SLOT_REG(i));  in hpc_release_ctlr()
570 		shpc_writel(ctrl, SLOT_REG(i), slot_reg);  in hpc_release_ctlr()
573 	cleanup_slots(ctrl);  in hpc_release_ctlr()
578 	serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in hpc_release_ctlr()
582 	shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in hpc_release_ctlr()
585 		del_timer(&ctrl->poll_timer);  in hpc_release_ctlr()
587 		free_irq(ctrl->pci_dev->irq, ctrl);  in hpc_release_ctlr()
588 		pci_disable_msi(ctrl->pci_dev);  in hpc_release_ctlr()
591 	iounmap(ctrl->creg);  in hpc_release_ctlr()
592 	release_mem_region(ctrl->mmio_base, ctrl->mmio_size);  in hpc_release_ctlr()
601 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in hpc_power_on_slot()
614 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in hpc_slot_enable()
627 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in hpc_slot_disable()
632 static int shpc_get_cur_bus_speed(struct controller *ctrl)  in shpc_get_cur_bus_speed()  argument
635 	struct pci_bus *bus = ctrl->pci_dev->subordinate;  in shpc_get_cur_bus_speed()
637 	u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);  in shpc_get_cur_bus_speed()
638 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in shpc_get_cur_bus_speed()
704 	struct controller *ctrl = slot->ctrl;  in hpc_set_bus_speed_mode()  local
707 	pi = shpc_readb(ctrl, PROG_INTERFACE);  in hpc_set_bus_speed_mode()
760 		ctrl_err(ctrl, "%s: Write command failed!\n", __func__);  in hpc_set_bus_speed_mode()
762 		shpc_get_cur_bus_speed(ctrl);  in hpc_set_bus_speed_mode()
769 	struct controller *ctrl = (struct controller *)dev_id;  in shpc_isr()  local
774 	intr_loc = shpc_readl(ctrl, INTR_LOC);  in shpc_isr()
778 	ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);  in shpc_isr()
785 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
788 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
790 		intr_loc2 = shpc_readl(ctrl, INTR_LOC);  in shpc_isr()
791 		ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);  in shpc_isr()
800 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
802 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
804 		wake_up_interruptible(&ctrl->queue);  in shpc_isr()
810 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_isr()
815 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_isr()
816 		ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",  in shpc_isr()
820 			shpchp_handle_switch_change(hp_slot, ctrl);  in shpc_isr()
823 			shpchp_handle_attention_button(hp_slot, ctrl);  in shpc_isr()
826 			shpchp_handle_presence_change(hp_slot, ctrl);  in shpc_isr()
829 			shpchp_handle_power_fault(hp_slot, ctrl);  in shpc_isr()
833 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_isr()
838 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
840 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
846 static int shpc_get_max_bus_speed(struct controller *ctrl)  in shpc_get_max_bus_speed()  argument
849 	struct pci_bus *bus = ctrl->pci_dev->subordinate;  in shpc_get_max_bus_speed()
851 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in shpc_get_max_bus_speed()
852 	u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);  in shpc_get_max_bus_speed()
853 	u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);  in shpc_get_max_bus_speed()
886 	ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);  in shpc_get_max_bus_speed()
914 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)  in shpc_init()  argument
922 	ctrl->pci_dev = pdev;  /* pci_dev of the P2P bridge */  in shpc_init()
923 	ctrl_dbg(ctrl, "Hotplug Controller:\n");  in shpc_init()
928 		ctrl->mmio_base = pci_resource_start(pdev, 0);  in shpc_init()
929 		ctrl->mmio_size = pci_resource_len(pdev, 0);  in shpc_init()
931 		ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);  in shpc_init()
932 		if (!ctrl->cap_offset) {  in shpc_init()
933 			ctrl_err(ctrl, "Cannot find PCI capability\n");  in shpc_init()
936 		ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);  in shpc_init()
938 		rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);  in shpc_init()
940 			ctrl_err(ctrl, "Cannot read base_offset\n");  in shpc_init()
944 		rc = shpc_indirect_read(ctrl, 3, &tempdword);  in shpc_init()
946 			ctrl_err(ctrl, "Cannot read slot config\n");  in shpc_init()
950 		ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);  in shpc_init()
953 			rc = shpc_indirect_read(ctrl, i, &tempdword);  in shpc_init()
955 				ctrl_err(ctrl, "Cannot read creg (index = %d)\n",  in shpc_init()
959 			ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);  in shpc_init()
962 		ctrl->mmio_base =  in shpc_init()
964 		ctrl->mmio_size = 0x24 + 0x4 * num_slots;  in shpc_init()
967 	ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",  in shpc_init()
973 		ctrl_err(ctrl, "pci_enable_device failed\n");  in shpc_init()
977 	if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {  in shpc_init()
978 		ctrl_err(ctrl, "Cannot reserve MMIO region\n");  in shpc_init()
983 	ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);  in shpc_init()
984 	if (!ctrl->creg) {  in shpc_init()
985 		ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",  in shpc_init()
986 			 ctrl->mmio_size, ctrl->mmio_base);  in shpc_init()
987 		release_mem_region(ctrl->mmio_base, ctrl->mmio_size);  in shpc_init()
991 	ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);  in shpc_init()
993 	mutex_init(&ctrl->crit_sect);  in shpc_init()
994 	mutex_init(&ctrl->cmd_lock);  in shpc_init()
997 	init_waitqueue_head(&ctrl->queue);  in shpc_init()
999 	ctrl->hpc_ops = &shpchp_hpc_ops;  in shpc_init()
1002 	slot_config = shpc_readl(ctrl, SLOT_CONFIG);  in shpc_init()
1003 	ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;  in shpc_init()
1004 	ctrl->num_slots = slot_config & SLOT_NUM;  in shpc_init()
1005 	ctrl->first_slot = (slot_config & PSN) >> 16;  in shpc_init()
1006 	ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;  in shpc_init()
1009 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1010 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1014 	shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);  in shpc_init()
1015 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1016 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1021 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_init()
1022 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_init()
1023 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",  in shpc_init()
1030 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_init()
1035 		timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);  in shpc_init()
1036 		start_int_poll_timer(ctrl, 10);  in shpc_init()
1041 			ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");  in shpc_init()
1042 			ctrl_info(ctrl, "Use INTx for the hotplug controller\n");  in shpc_init()
1047 		rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,  in shpc_init()
1048 				 MY_NAME, (void *)ctrl);  in shpc_init()
1049 		ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",  in shpc_init()
1050 			 ctrl->pci_dev->irq, rc);  in shpc_init()
1052 			ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",  in shpc_init()
1053 				 ctrl->pci_dev->irq);  in shpc_init()
1057 	ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);  in shpc_init()
1059 	shpc_get_max_bus_speed(ctrl);  in shpc_init()
1060 	shpc_get_cur_bus_speed(ctrl);  in shpc_init()
1065 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_init()
1066 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_init()
1067 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",  in shpc_init()
1072 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_init()
1076 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1079 		shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);  in shpc_init()
1080 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1081 		ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1088 	iounmap(ctrl->creg);  in shpc_init()