351 	u32 val, status_l0, status_l1;  in tegra_pcie_rp_irq_handler()  local
356 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);  in tegra_pcie_rp_irq_handler()
357 		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);  in tegra_pcie_rp_irq_handler()
359 		    status_l1 & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {  in tegra_pcie_rp_irq_handler()
376 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);  in tegra_pcie_rp_irq_handler()
377 		if (status_l1 & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {  in tegra_pcie_rp_irq_handler()
383 		if (status_l1 & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {  in tegra_pcie_rp_irq_handler()
402 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_18);  in tegra_pcie_rp_irq_handler()
404 		if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {  in tegra_pcie_rp_irq_handler()
408 		if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {  in tegra_pcie_rp_irq_handler()
412 		if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {  in tegra_pcie_rp_irq_handler()
504 	u32 status_l0, status_l1, link_status;  in tegra_pcie_ep_hard_irq()  local
508 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);  in tegra_pcie_ep_hard_irq()
509 		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);  in tegra_pcie_ep_hard_irq()
511 		if (status_l1 & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)  in tegra_pcie_ep_hard_irq()
514 		if (status_l1 & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {  in tegra_pcie_ep_hard_irq()
526 		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);  in tegra_pcie_ep_hard_irq()
527 		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);  in tegra_pcie_ep_hard_irq()
529 		if (status_l1 & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)  in tegra_pcie_ep_hard_irq()