51 static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,  in meson_mx_efuse_mask_bits()  argument
56 	data = readl(efuse->base + reg);  in meson_mx_efuse_mask_bits()
60 	writel(data, efuse->base + reg);  in meson_mx_efuse_mask_bits()
63 static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)  in meson_mx_efuse_hw_enable()  argument
67 	err = clk_prepare_enable(efuse->core_clk);  in meson_mx_efuse_hw_enable()
72 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_hw_enable()
75 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,  in meson_mx_efuse_hw_enable()
81 static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)  in meson_mx_efuse_hw_disable()  argument
83 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_hw_disable()
87 	clk_disable_unprepare(efuse->core_clk);  in meson_mx_efuse_hw_disable()
90 static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,  in meson_mx_efuse_read_addr()  argument
98 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_read_addr()
102 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_read_addr()
105 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_read_addr()
109 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_read_addr()
112 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_read_addr()
119 	readl(efuse->base + MESON_MX_EFUSE_CNTL1);  in meson_mx_efuse_read_addr()
121 	err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_read_addr()
126 		dev_err(efuse->config.dev,  in meson_mx_efuse_read_addr()
131 	*value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);  in meson_mx_efuse_read_addr()
139 	struct meson_mx_efuse *efuse = context;  in meson_mx_efuse_read()  local
143 	err = meson_mx_efuse_hw_enable(efuse);  in meson_mx_efuse_read()
147 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_read()
151 	for (i = 0; i < bytes; i += efuse->config.word_size) {  in meson_mx_efuse_read()
152 		addr = (offset + i) / efuse->config.word_size;  in meson_mx_efuse_read()
154 		err = meson_mx_efuse_read_addr(efuse, addr, &tmp);  in meson_mx_efuse_read()
159 		       min_t(size_t, bytes - i, efuse->config.word_size));  in meson_mx_efuse_read()
162 	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,  in meson_mx_efuse_read()
165 	meson_mx_efuse_hw_disable(efuse);  in meson_mx_efuse_read()
196 	struct meson_mx_efuse *efuse;  in meson_mx_efuse_probe()  local
203 	efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);  in meson_mx_efuse_probe()
204 	if (!efuse)  in meson_mx_efuse_probe()
208 	efuse->base = devm_ioremap_resource(&pdev->dev, res);  in meson_mx_efuse_probe()
209 	if (IS_ERR(efuse->base))  in meson_mx_efuse_probe()
210 		return PTR_ERR(efuse->base);  in meson_mx_efuse_probe()
212 	efuse->config.name = drvdata->name;  in meson_mx_efuse_probe()
213 	efuse->config.owner = THIS_MODULE;  in meson_mx_efuse_probe()
214 	efuse->config.dev = &pdev->dev;  in meson_mx_efuse_probe()
215 	efuse->config.priv = efuse;  in meson_mx_efuse_probe()
216 	efuse->config.stride = drvdata->word_size;  in meson_mx_efuse_probe()
217 	efuse->config.word_size = drvdata->word_size;  in meson_mx_efuse_probe()
218 	efuse->config.size = SZ_512;  in meson_mx_efuse_probe()
219 	efuse->config.read_only = true;  in meson_mx_efuse_probe()
220 	efuse->config.reg_read = meson_mx_efuse_read;  in meson_mx_efuse_probe()
222 	efuse->core_clk = devm_clk_get(&pdev->dev, "core");  in meson_mx_efuse_probe()
223 	if (IS_ERR(efuse->core_clk)) {  in meson_mx_efuse_probe()
225 		return PTR_ERR(efuse->core_clk);  in meson_mx_efuse_probe()
228 	efuse->nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);  in meson_mx_efuse_probe()
230 	return PTR_ERR_OR_ZERO(efuse->nvmem);  in meson_mx_efuse_probe()