67 void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio)  in ipc_mmio_update_cp_capability()  argument
72 	ver = ipc_mmio_get_cp_version(ipc_mmio);  in ipc_mmio_update_cp_capability()
73 	cp_cap = ioread32(ipc_mmio->base + ipc_mmio->offset.cp_capability);  in ipc_mmio_update_cp_capability()
75 	ipc_mmio->mux_protocol = ((ver >= IOSM_CP_VERSION) && (cp_cap &  in ipc_mmio_update_cp_capability()
79 	ipc_mmio->has_ul_flow_credit =  in ipc_mmio_update_cp_capability()
85 	struct iosm_mmio *ipc_mmio = kzalloc(sizeof(*ipc_mmio), GFP_KERNEL);  in ipc_mmio_init()  local
89 	if (!ipc_mmio)  in ipc_mmio_init()
92 	ipc_mmio->dev = dev;  in ipc_mmio_init()
94 	ipc_mmio->base = mmio;  in ipc_mmio_init()
96 	ipc_mmio->offset.exec_stage = MMIO_OFFSET_EXECUTION_STAGE;  in ipc_mmio_init()
102 		stage = ipc_mmio_get_exec_stage(ipc_mmio);  in ipc_mmio_init()
110 		dev_err(ipc_mmio->dev, "invalid exec stage %X", stage);  in ipc_mmio_init()
114 	ipc_mmio->offset.chip_info = MMIO_OFFSET_CHIP_INFO;  in ipc_mmio_init()
117 	ipc_mmio->chip_info_version =  in ipc_mmio_init()
118 		ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info);  in ipc_mmio_init()
123 	ipc_mmio->chip_info_size =  in ipc_mmio_init()
124 		ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info + 1) + 2;  in ipc_mmio_init()
126 	if (ipc_mmio->chip_info_size != MMIO_CHIP_INFO_SIZE) {  in ipc_mmio_init()
127 		dev_err(ipc_mmio->dev, "Unexpected Chip Info");  in ipc_mmio_init()
131 	ipc_mmio->offset.rom_exit_code = MMIO_OFFSET_ROM_EXIT_CODE;  in ipc_mmio_init()
133 	ipc_mmio->offset.psi_address = MMIO_OFFSET_PSI_ADDRESS;  in ipc_mmio_init()
134 	ipc_mmio->offset.psi_size = MMIO_OFFSET_PSI_SIZE;  in ipc_mmio_init()
135 	ipc_mmio->offset.ipc_status = MMIO_OFFSET_IPC_STATUS;  in ipc_mmio_init()
136 	ipc_mmio->offset.context_info = MMIO_OFFSET_CONTEXT_INFO;  in ipc_mmio_init()
137 	ipc_mmio->offset.ap_win_base = MMIO_OFFSET_BASE_ADDR;  in ipc_mmio_init()
138 	ipc_mmio->offset.ap_win_end = MMIO_OFFSET_END_ADDR;  in ipc_mmio_init()
140 	ipc_mmio->offset.cp_version = MMIO_OFFSET_CP_VERSION;  in ipc_mmio_init()
141 	ipc_mmio->offset.cp_capability = MMIO_OFFSET_CP_CAPABILITIES;  in ipc_mmio_init()
143 	return ipc_mmio;  in ipc_mmio_init()
146 	kfree(ipc_mmio);  in ipc_mmio_init()
150 enum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio)  in ipc_mmio_get_exec_stage()  argument
152 	if (!ipc_mmio)  in ipc_mmio_get_exec_stage()
155 	return (enum ipc_mem_exec_stage)ioread32(ipc_mmio->base +  in ipc_mmio_get_exec_stage()
156 						 ipc_mmio->offset.exec_stage);  in ipc_mmio_get_exec_stage()
159 void ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest,  in ipc_mmio_copy_chip_info()  argument
162 	if (ipc_mmio && dest)  in ipc_mmio_copy_chip_info()
163 		memcpy_fromio(dest, ipc_mmio->base + ipc_mmio->offset.chip_info,  in ipc_mmio_copy_chip_info()
167 enum ipc_mem_device_ipc_state ipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio)  in ipc_mmio_get_ipc_state()  argument
169 	if (!ipc_mmio)  in ipc_mmio_get_ipc_state()
172 	return (enum ipc_mem_device_ipc_state)ioread32(ipc_mmio->base +  in ipc_mmio_get_ipc_state()
173 						       ipc_mmio->offset.ipc_status);  in ipc_mmio_get_ipc_state()
176 enum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio)  in ipc_mmio_get_rom_exit_code()  argument
178 	if (!ipc_mmio)  in ipc_mmio_get_rom_exit_code()
181 	return (enum rom_exit_code)ioread32(ipc_mmio->base +  in ipc_mmio_get_rom_exit_code()
182 					    ipc_mmio->offset.rom_exit_code);  in ipc_mmio_get_rom_exit_code()
185 void ipc_mmio_config(struct iosm_mmio *ipc_mmio)  in ipc_mmio_config()  argument
187 	if (!ipc_mmio)  in ipc_mmio_config()
193 	iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_base);  in ipc_mmio_config()
194 	iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_end);  in ipc_mmio_config()
196 	iowrite64(ipc_mmio->context_info_addr,  in ipc_mmio_config()
197 		  ipc_mmio->base + ipc_mmio->offset.context_info);  in ipc_mmio_config()
200 void ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr,  in ipc_mmio_set_psi_addr_and_size()  argument
203 	if (!ipc_mmio)  in ipc_mmio_set_psi_addr_and_size()
206 	iowrite64(addr, ipc_mmio->base + ipc_mmio->offset.psi_address);  in ipc_mmio_set_psi_addr_and_size()
207 	iowrite32(size, ipc_mmio->base + ipc_mmio->offset.psi_size);  in ipc_mmio_set_psi_addr_and_size()
210 void ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio, phys_addr_t addr)  in ipc_mmio_set_contex_info_addr()  argument
212 	if (!ipc_mmio)  in ipc_mmio_set_contex_info_addr()
218 	ipc_mmio->context_info_addr = addr;  in ipc_mmio_set_contex_info_addr()
221 int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio)  in ipc_mmio_get_cp_version()  argument
223 	if (ipc_mmio)  in ipc_mmio_get_cp_version()
224 		return ioread32(ipc_mmio->base + ipc_mmio->offset.cp_version);  in ipc_mmio_get_cp_version()