156 	rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,  in rtw8723d_phy_set_param()
201 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);  in rtw8723d_phy_set_param()
202 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);  in rtw8723d_phy_set_param()
395 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);  in rtw8723d_cfg_notch()
396 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8723d_cfg_notch()
401 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8723d_cfg_notch()
407 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);  in rtw8723d_cfg_notch()
408 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8723d_cfg_notch()
413 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8723d_cfg_notch()
416 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);  in rtw8723d_cfg_notch()
417 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8723d_cfg_notch()
422 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8723d_cfg_notch()
425 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8723d_cfg_notch()
426 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8723d_cfg_notch()
500 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8723d_set_channel_bb()
501 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8723d_set_channel_bb()
502 		rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1);  in rtw8723d_set_channel_bb()
503 		rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa);  in rtw8723d_set_channel_bb()
506 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8723d_set_channel_bb()
507 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8723d_set_channel_bb()
508 		rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0);  in rtw8723d_set_channel_bb()
509 		rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND,  in rtw8723d_set_channel_bb()
595 		rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index);  in rtw8723d_set_tx_power_index_by_rate()
631 	rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1);  in rtw8723d_false_alarm_statistics()
632 	rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1);  in rtw8723d_false_alarm_statistics()
633 	rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1);  in rtw8723d_false_alarm_statistics()
634 	rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1);  in rtw8723d_false_alarm_statistics()
672 	rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1);  in rtw8723d_false_alarm_statistics()
673 	rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0);  in rtw8723d_false_alarm_statistics()
674 	rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1);  in rtw8723d_false_alarm_statistics()
675 	rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0);  in rtw8723d_false_alarm_statistics()
676 	rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0);  in rtw8723d_false_alarm_statistics()
677 	rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0);  in rtw8723d_false_alarm_statistics()
678 	rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0);  in rtw8723d_false_alarm_statistics()
679 	rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2);  in rtw8723d_false_alarm_statistics()
680 	rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0);  in rtw8723d_false_alarm_statistics()
681 	rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2);  in rtw8723d_false_alarm_statistics()
682 	rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1);  in rtw8723d_false_alarm_statistics()
683 	rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0);  in rtw8723d_false_alarm_statistics()
757 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);  in rtw8723d_iqk_restore_regs()
758 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia);  in rtw8723d_iqk_restore_regs()
760 	rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50);  in rtw8723d_iqk_restore_regs()
761 	rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib);  in rtw8723d_iqk_restore_regs()
777 	rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1);  in rtw8723d_iqk_config_path_ctrl()
805 	rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1);  in rtw8723d_iqk_config_lte_path_gnt()
921 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);  in rtw8723d_iqk_one_shot()
950 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);  in rtw8723d_iqk_txrx_path_post()
969 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);  in rtw8723d_iqk_tx_path()
1030 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);  in rtw8723d_iqk_rx_path()
1100 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);  in rtw8723d_iqk_rx_path()
1140 	rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,  in rtw8723d_iqk_fill_s1_matrix()
1142 	rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,  in rtw8723d_iqk_fill_s1_matrix()
1147 	rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,  in rtw8723d_iqk_fill_s1_matrix()
1149 	rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,  in rtw8723d_iqk_fill_s1_matrix()
1151 	rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,  in rtw8723d_iqk_fill_s1_matrix()
1163 	rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X,  in rtw8723d_iqk_fill_s1_matrix()
1165 	rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1,  in rtw8723d_iqk_fill_s1_matrix()
1167 	rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2,  in rtw8723d_iqk_fill_s1_matrix()
1187 	rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a);  in rtw8723d_iqk_fill_s0_matrix()
1188 	rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext);  in rtw8723d_iqk_fill_s0_matrix()
1193 	rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c);  in rtw8723d_iqk_fill_s0_matrix()
1194 	rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext);  in rtw8723d_iqk_fill_s0_matrix()
1199 	rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0,  in rtw8723d_iqk_fill_s0_matrix()
1201 	rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0,  in rtw8723d_iqk_fill_s0_matrix()
1224 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);  in rtw8723d_iqk_rf_standby()
1227 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);  in rtw8723d_iqk_rf_standby()
1296 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);  in rtw8723d_iqk_precfg_path()
1318 	rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);  in rtw8723d_iqk_one_round()
1401 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);  in rtw8723d_iqk_one_round()
1525 	rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);  in rtw8723d_phy_cck_pd_set()
1526 	rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,  in rtw8723d_phy_cck_pd_set()
1728 		rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,  in rtw8723d_set_iqk_matrix_by_result()
1738 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D);  in rtw8723d_set_iqk_matrix_by_result()
1739 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C);  in rtw8723d_set_iqk_matrix_by_result()
1740 		rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A);  in rtw8723d_set_iqk_matrix_by_result()
1742 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0,  in rtw8723d_set_iqk_matrix_by_result()
1744 		rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0,  in rtw8723d_set_iqk_matrix_by_result()
1746 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0,  in rtw8723d_set_iqk_matrix_by_result()
1775 		rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,  in rtw8723d_set_iqk_matrix()
1784 		rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0,  in rtw8723d_set_iqk_matrix()
1786 		rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0,  in rtw8723d_set_iqk_matrix()
1788 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0,  in rtw8723d_set_iqk_matrix()
1790 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0,  in rtw8723d_set_iqk_matrix()
1792 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0);  in rtw8723d_set_iqk_matrix()
1793 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0);  in rtw8723d_set_iqk_matrix()
1794 		rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0);  in rtw8723d_set_iqk_matrix()
1817 	rtw_write32_mask(rtwdev, 0xab4, 0x000007FF,  in rtw8723d_pwrtrack_set_cck_pwr()
1874 	rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,  in rtw8723d_pwrtrack_set_xtal()