67 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in rtl8723_phy_rf_serial_read()
119 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in rtl8723_phy_rf_serial_write()
165 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in rtl8723_phy_init_bb_rf_reg_def()
166 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in rtl8723_phy_init_bb_rf_reg_def()
167 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in rtl8723_phy_init_bb_rf_reg_def()
168 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in rtl8723_phy_init_bb_rf_reg_def()
170 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in rtl8723_phy_init_bb_rf_reg_def()
171 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in rtl8723_phy_init_bb_rf_reg_def()
172 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in rtl8723_phy_init_bb_rf_reg_def()
173 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in rtl8723_phy_init_bb_rf_reg_def()
175 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;  in rtl8723_phy_init_bb_rf_reg_def()
176 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in rtl8723_phy_init_bb_rf_reg_def()
178 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;  in rtl8723_phy_init_bb_rf_reg_def()
179 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in rtl8723_phy_init_bb_rf_reg_def()
181 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =  in rtl8723_phy_init_bb_rf_reg_def()
183 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in rtl8723_phy_init_bb_rf_reg_def()
186 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in rtl8723_phy_init_bb_rf_reg_def()
187 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in rtl8723_phy_init_bb_rf_reg_def()
188 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in rtl8723_phy_init_bb_rf_reg_def()
189 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in rtl8723_phy_init_bb_rf_reg_def()
191 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in rtl8723_phy_init_bb_rf_reg_def()
192 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in rtl8723_phy_init_bb_rf_reg_def()
193 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in rtl8723_phy_init_bb_rf_reg_def()
194 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in rtl8723_phy_init_bb_rf_reg_def()
196 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;  in rtl8723_phy_init_bb_rf_reg_def()
197 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;  in rtl8723_phy_init_bb_rf_reg_def()
199 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;  in rtl8723_phy_init_bb_rf_reg_def()
200 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in rtl8723_phy_init_bb_rf_reg_def()
202 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;  in rtl8723_phy_init_bb_rf_reg_def()
203 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;  in rtl8723_phy_init_bb_rf_reg_def()
204 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;  in rtl8723_phy_init_bb_rf_reg_def()
205 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;  in rtl8723_phy_init_bb_rf_reg_def()
207 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;  in rtl8723_phy_init_bb_rf_reg_def()
208 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;  in rtl8723_phy_init_bb_rf_reg_def()
209 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;  in rtl8723_phy_init_bb_rf_reg_def()
210 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;  in rtl8723_phy_init_bb_rf_reg_def()
212 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;  in rtl8723_phy_init_bb_rf_reg_def()
213 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;  in rtl8723_phy_init_bb_rf_reg_def()
214 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;  in rtl8723_phy_init_bb_rf_reg_def()
215 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;  in rtl8723_phy_init_bb_rf_reg_def()
217 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;  in rtl8723_phy_init_bb_rf_reg_def()
218 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;  in rtl8723_phy_init_bb_rf_reg_def()
219 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;  in rtl8723_phy_init_bb_rf_reg_def()
220 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;  in rtl8723_phy_init_bb_rf_reg_def()
222 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
223 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
224 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
225 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
227 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;  in rtl8723_phy_init_bb_rf_reg_def()
228 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;  in rtl8723_phy_init_bb_rf_reg_def()
229 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;  in rtl8723_phy_init_bb_rf_reg_def()
230 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;  in rtl8723_phy_init_bb_rf_reg_def()
232 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
233 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
234 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
235 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;  in rtl8723_phy_init_bb_rf_reg_def()
237 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;  in rtl8723_phy_init_bb_rf_reg_def()
238 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in rtl8723_phy_init_bb_rf_reg_def()
239 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;  in rtl8723_phy_init_bb_rf_reg_def()
240 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;  in rtl8723_phy_init_bb_rf_reg_def()
242 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;  in rtl8723_phy_init_bb_rf_reg_def()
243 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;  in rtl8723_phy_init_bb_rf_reg_def()