92 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,  in _rtl92s_phy_rf_serial_read()
97 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);  in _rtl92s_phy_rf_serial_read()
100 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |  in _rtl92s_phy_rf_serial_read()
142 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);  in _rtl92s_phy_rf_serial_write()
269 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);  in rtl92s_phy_set_bw_mode()
270 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);  in rtl92s_phy_set_bw_mode()
276 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);  in rtl92s_phy_set_bw_mode()
277 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);  in rtl92s_phy_set_bw_mode()
279 		rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,  in rtl92s_phy_set_bw_mode()
281 		rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);  in rtl92s_phy_set_bw_mode()
1267 		rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);  in _rtl92s_phy_set_fwcmd_io()
1268 		rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);  in _rtl92s_phy_set_fwcmd_io()
1270 		rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);  in _rtl92s_phy_set_fwcmd_io()
1274 		rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);  in _rtl92s_phy_set_fwcmd_io()
1282 		rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);  in _rtl92s_phy_set_fwcmd_io()
1283 		rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);  in _rtl92s_phy_set_fwcmd_io()
1285 		rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);  in _rtl92s_phy_set_fwcmd_io()
1293 		rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);  in _rtl92s_phy_set_fwcmd_io()