Lines Matching refs:rtl_set_bbreg
265 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
268 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92d_phy_rf_serial_read()
271 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
304 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92d_phy_rf_serial_write()
549 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
560 rtl_set_bbreg(hw, agctab_array_table[i], in _rtl92d_phy_config_bb_with_headerfile()
576 rtl_set_bbreg(hw, agctab_array_table[i], in _rtl92d_phy_config_bb_with_headerfile()
591 rtl_set_bbreg(hw, in _rtl92d_phy_config_bb_with_headerfile()
975 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
976 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
978 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | in rtl92d_phy_set_bw_mode()
982 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
983 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
988 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, in rtl92d_phy_set_bw_mode()
992 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl92d_phy_set_bw_mode()
994 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | in rtl92d_phy_set_bw_mode()
996 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92d_phy_set_bw_mode()
1013 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1014 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1015 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); in _rtl92d_phy_stop_trx_before_changeband()
1016 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); in _rtl92d_phy_stop_trx_before_changeband()
1048 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92d_phy_switch_wirelessband()
1049 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92d_phy_switch_wirelessband()
1084 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1085 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
1088 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | in _rtl92d_phy_reload_imr_setting()
1091 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | in _rtl92d_phy_reload_imr_setting()
1100 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
1101 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1); in _rtl92d_phy_reload_imr_setting()
1113 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1114 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, in _rtl92d_phy_reload_imr_setting()
1123 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, in _rtl92d_phy_reload_imr_setting()
1125 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3); in _rtl92d_phy_reload_imr_setting()
1153 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); in _rtl92d_phy_enable_rf_env()
1156 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); in _rtl92d_phy_enable_rf_env()
1160 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1163 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1180 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); in _rtl92d_phy_restore_rf_env()
1184 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, in _rtl92d_phy_restore_rf_env()
1394 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1395 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1397 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1398 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1400 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1401 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1404 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1405 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1406 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1407 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1411 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
1414 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
1415 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
1464 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1465 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1466 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
1467 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
1470 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1471 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1472 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
1473 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
1477 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
1479 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
1480 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
1485 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
1486 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
1521 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1523 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1538 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1539 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1581 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1582 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1583 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1584 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1587 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1588 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1589 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1590 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1594 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1597 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1598 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1604 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1605 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1639 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1641 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1680 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); in _rtl92d_phy_reload_adda_registers()
1708 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); in _rtl92d_phy_path_adda_on()
1731 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1732 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1733 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1744 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1745 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1798 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate()
1799 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1800 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1801 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1802 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate()
1804 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1806 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1813 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1815 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1818 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1819 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1820 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1885 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1905 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1906 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1972 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate_5g_normal()
1973 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
1974 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
1975 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
1976 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate_5g_normal()
1979 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1981 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1984 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
1985 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
1986 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
2041 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
2149 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92d_phy_patha_fill_iqk_matrix()
2150 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), in _rtl92d_phy_patha_fill_iqk_matrix()
2163 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92d_phy_patha_fill_iqk_matrix()
2165 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_patha_fill_iqk_matrix()
2168 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), in _rtl92d_phy_patha_fill_iqk_matrix()
2178 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2180 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2182 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2207 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92d_phy_pathb_fill_iqk_matrix()
2208 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), in _rtl92d_phy_pathb_fill_iqk_matrix()
2218 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2220 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2222 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), in _rtl92d_phy_pathb_fill_iqk_matrix()
2227 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2229 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2231 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2540 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); in _rtl92d_phy_lc_calibrate_sw()
2620 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); in _rtl92d_phy_lc_calibrate_sw()
3333 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); in rtl92d_update_bbrf_configuration()
3334 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); in rtl92d_update_bbrf_configuration()
3336 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); in rtl92d_update_bbrf_configuration()
3337 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); in rtl92d_update_bbrf_configuration()
3340 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); in rtl92d_update_bbrf_configuration()
3342 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); in rtl92d_update_bbrf_configuration()
3344 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); in rtl92d_update_bbrf_configuration()
3346 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3348 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3351 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
3356 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in rtl92d_update_bbrf_configuration()
3361 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); in rtl92d_update_bbrf_configuration()
3363 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
3372 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in rtl92d_update_bbrf_configuration()
3377 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in rtl92d_update_bbrf_configuration()
3382 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92d_update_bbrf_configuration()
3388 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); in rtl92d_update_bbrf_configuration()
3389 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); in rtl92d_update_bbrf_configuration()
3391 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); in rtl92d_update_bbrf_configuration()
3392 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); in rtl92d_update_bbrf_configuration()
3395 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); in rtl92d_update_bbrf_configuration()
3397 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); in rtl92d_update_bbrf_configuration()
3399 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); in rtl92d_update_bbrf_configuration()
3402 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3405 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3408 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3411 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3414 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
3417 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), in rtl92d_update_bbrf_configuration()
3419 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), in rtl92d_update_bbrf_configuration()
3422 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
3427 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), in rtl92d_update_bbrf_configuration()
3429 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), in rtl92d_update_bbrf_configuration()
3431 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92d_update_bbrf_configuration()
3438 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3439 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3440 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3441 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | in rtl92d_update_bbrf_configuration()
3443 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3444 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3445 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); in rtl92d_update_bbrf_configuration()
3468 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); in rtl92d_update_bbrf_configuration()
3469 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); in rtl92d_update_bbrf_configuration()
3473 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | in rtl92d_update_bbrf_configuration()
3490 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); in rtl92d_update_bbrf_configuration()
3491 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); in rtl92d_update_bbrf_configuration()
3493 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); in rtl92d_update_bbrf_configuration()