Lines Matching refs:iwl_write32
462 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue)); in iwl_pcie_clear_irq()
549 iwl_write32(trans, CSR_INT_MASK, 0x00000000); in _iwl_disable_interrupts()
553 iwl_write32(trans, CSR_INT, 0xffffffff); in _iwl_disable_interrupts()
554 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); in _iwl_disable_interrupts()
557 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, in _iwl_disable_interrupts()
559 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, in _iwl_disable_interrupts()
616 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in _iwl_enable_interrupts()
624 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, in _iwl_enable_interrupts()
626 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, in _iwl_enable_interrupts()
643 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); in iwl_enable_hw_int_msk_msix()
651 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); in iwl_enable_fh_int_msk_msix()
662 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_fw_load_int()
664 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, in iwl_enable_fw_load_int()
686 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_fw_load_int_ctx_info()
728 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_rfkill_int()
730 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, in iwl_enable_rfkill_int()
774 iwl_write32(trans, reg, v); in __iwl_trans_pcie_set_bits_mask()