Lines Matching refs:prph_sc_ctrl
84 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; in iwl_pcie_ctxt_info_gen3_init() local
118 prph_sc_ctrl = &prph_scratch->ctrl_cfg; in iwl_pcie_ctxt_info_gen3_init()
120 prph_sc_ctrl->version.version = 0; in iwl_pcie_ctxt_info_gen3_init()
121 prph_sc_ctrl->version.mac_id = in iwl_pcie_ctxt_info_gen3_init()
123 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); in iwl_pcie_ctxt_info_gen3_init()
132 prph_sc_ctrl->rbd_cfg.free_rbd_addr = in iwl_pcie_ctxt_info_gen3_init()
135 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, in iwl_pcie_ctxt_info_gen3_init()
137 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); in iwl_pcie_ctxt_info_gen3_init()
284 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = in iwl_trans_pcie_ctx_info_gen3_set_pnvm() local
293 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) in iwl_trans_pcie_ctx_info_gen3_set_pnvm()
305 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = in iwl_trans_pcie_ctx_info_gen3_set_pnvm()
307 prph_sc_ctrl->pnvm_cfg.pnvm_size = in iwl_trans_pcie_ctx_info_gen3_set_pnvm()
317 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = in iwl_trans_pcie_ctx_info_gen3_set_reduce_power() local
326 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) in iwl_trans_pcie_ctx_info_gen3_set_reduce_power()
339 prph_sc_ctrl->reduce_power_cfg.base_addr = in iwl_trans_pcie_ctx_info_gen3_set_reduce_power()
341 prph_sc_ctrl->reduce_power_cfg.size = in iwl_trans_pcie_ctx_info_gen3_set_reduce_power()