474 	b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);  in b43_ram_write()
475 	b43_write32(dev, B43_MMIO_RAM_DATA, val);  in b43_ram_write()
487 	b43_write32(dev, B43_MMIO_SHM_CONTROL, control);  in b43_shm_control_word()
551 	b43_write32(dev, B43_MMIO_SHM_DATA, value);  in b43_shm_write32()
644 	b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);  in b43_tsf_write_locked()
645 	b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);  in b43_tsf_write_locked()
1187 	b43_write32(dev, B43_MMIO_MACCTL, macctl);  in b43_power_saving_ctl_bits()
1330 	b43_write32(dev, B43_MMIO_MACCTL, macctl);  in b43_wireless_core_reset()
1400 	b43_write32(dev, B43_MMIO_MACCMD,  in b43_generate_noise_sample()
1503 		b43_write32(dev, B43_MMIO_MACCMD,  in handle_irq_atim_end()
1748 		b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);  in handle_irq_beacon()
1761 		b43_write32(dev, B43_MMIO_MACCMD, cmd);  in handle_irq_beacon()
1767 			b43_write32(dev, B43_MMIO_MACCMD, cmd);  in handle_irq_beacon()
1772 			b43_write32(dev, B43_MMIO_MACCMD, cmd);  in handle_irq_beacon()
1787 			b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);  in b43_do_beacon_update_trigger_work()
1856 		b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));  in b43_set_beacon_int()
1857 		b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));  in b43_set_beacon_int()
2045 	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);  in b43_do_interrupt_thread()
2100 	b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);  in b43_do_interrupt()
2101 	b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);  in b43_do_interrupt()
2102 	b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);  in b43_do_interrupt()
2103 	b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);  in b43_do_interrupt()
2104 	b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);  in b43_do_interrupt()
2105 	b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);  in b43_do_interrupt()
2111 	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);  in b43_do_interrupt()
2620 	b43_write32(dev, B43_MMIO_MACCTL, macctl);  in b43_upload_microcode()
2632 		b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));  in b43_upload_microcode()
2641 		b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);  in b43_upload_microcode()
2645 			b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));  in b43_upload_microcode()
2650 	b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);  in b43_upload_microcode()
2782 			b43_write32(dev, offset, value);  in b43_write_initvals()
2967 		b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,  in b43_mac_enable()
3130 	b43_write32(dev, B43_MMIO_MACCTL, ctl);  in b43_adjust_opmode()
3250 	b43_write32(dev, B43_MMIO_MACCTL, macctl);  in b43_chip_init()
3288 	b43_write32(dev, 0x0100, 0x01000000);  in b43_chip_init()
3290 		b43_write32(dev, 0x010C, 0x01000000);  in b43_chip_init()
3308 		b43_write32(dev, 0x0188, 0x80000000);  in b43_chip_init()
3309 		b43_write32(dev, 0x018C, 0x02000000);  in b43_chip_init()
3311 	b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);  in b43_chip_init()
3312 	b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);  in b43_chip_init()
3313 	b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);  in b43_chip_init()
3314 	b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);  in b43_chip_init()
3315 	b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);  in b43_chip_init()
3316 	b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);  in b43_chip_init()
3317 	b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);  in b43_chip_init()
3501 		b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);  in b43_validate_chipaccess()
3507 	b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);  in b43_validate_chipaccess()
4352 		b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);  in b43_wireless_core_stop()
4356 		b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);  in b43_wireless_core_stop()
4427 	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);  in b43_wireless_core_start()