77 	wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),  in wil6210_mask_irq_tx()
83 	wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMS),  in wil6210_mask_irq_tx_edma()
89 	wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),  in wil6210_mask_irq_rx()
95 	wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMS),  in wil6210_mask_irq_rx_edma()
104 	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),  in wil6210_mask_irq_misc()
112 	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),  in wil6210_mask_halp()
120 	wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);  in wil6210_mask_irq_pseudo()
127 	wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),  in wil6210_unmask_irq_tx()
133 	wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMC),  in wil6210_unmask_irq_tx_edma()
141 	wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),  in wil6210_unmask_irq_rx()
147 	wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMC),  in wil6210_unmask_irq_rx_edma()
156 	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),  in wil6210_unmask_irq_misc()
164 	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),  in wil6210_unmask_halp()
174 	wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);  in wil6210_unmask_irq_pseudo()
193 	wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),  in wil_unmask_irq()
195 	wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),  in wil_unmask_irq()
197 	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),  in wil_unmask_irq()
199 	wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, ICC),  in wil_unmask_irq()
201 	wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, ICC),  in wil_unmask_irq()
226 	wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_0, moderation);  in wil_configure_interrupt_moderation_edma()
227 	wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_1, moderation);  in wil_configure_interrupt_moderation_edma()
249 	wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);  in wil_configure_interrupt_moderation()
250 	wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);  in wil_configure_interrupt_moderation()
254 	wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,  in wil_configure_interrupt_moderation()
258 	wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);  in wil_configure_interrupt_moderation()
259 	wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);  in wil_configure_interrupt_moderation()
263 	wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |  in wil_configure_interrupt_moderation()
267 	wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);  in wil_configure_interrupt_moderation()
268 	wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);  in wil_configure_interrupt_moderation()
272 	wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,  in wil_configure_interrupt_moderation()
276 	wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);  in wil_configure_interrupt_moderation()
277 	wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);  in wil_configure_interrupt_moderation()
281 	wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |  in wil_configure_interrupt_moderation()
861 	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),  in wil6210_set_halp()
869 	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),  in wil6210_clear_halp()