Lines Matching refs:ah
33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
39 static void ath9k_hw_set_clockrate(struct ath_hw *ah) in ath9k_hw_set_clockrate() argument
41 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_clockrate()
42 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_clockrate()
46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) in ath9k_hw_set_clockrate()
52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
69 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) in ath9k_hw_mac_to_clks() argument
71 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_mac_to_clks()
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) in ath9k_hw_wait() argument
83 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
89 ath_dbg(ath9k_hw_common(ah), ANY, in ath9k_hw_wait()
91 timeout, reg, REG_READ(ah, reg), mask, val); in ath9k_hw_wait()
97 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_synth_delay() argument
110 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, in ath9k_hw_write_array() argument
115 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_write_array()
117 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
121 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_write_array()
124 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) in ath9k_hw_read_array() argument
131 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); in ath9k_hw_read_array()
137 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); in ath9k_hw_read_array()
144 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); in ath9k_hw_read_array()
166 u16 ath9k_hw_computetxtime(struct ath_hw *ah, in ath9k_hw_computetxtime() argument
185 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
193 } else if (ah->curchan && in ath9k_hw_computetxtime()
194 IS_CHAN_HALF_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
211 ath_err(ath9k_hw_common(ah), in ath9k_hw_computetxtime()
221 void ath9k_hw_get_channel_centers(struct ath_hw *ah, in ath9k_hw_get_channel_centers() argument
254 static bool ath9k_hw_read_revisions(struct ath_hw *ah) in ath9k_hw_read_revisions() argument
259 if (ah->get_mac_revision) in ath9k_hw_read_revisions()
260 ah->hw_version.macRev = ah->get_mac_revision(); in ath9k_hw_read_revisions()
262 switch (ah->hw_version.devid) { in ath9k_hw_read_revisions()
264 ah->hw_version.macVersion = AR_SREV_VERSION_9100; in ath9k_hw_read_revisions()
267 ah->hw_version.macVersion = AR_SREV_VERSION_9330; in ath9k_hw_read_revisions()
268 if (!ah->get_mac_revision) { in ath9k_hw_read_revisions()
269 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340; in ath9k_hw_read_revisions()
277 ah->hw_version.macVersion = AR_SREV_VERSION_9550; in ath9k_hw_read_revisions()
280 ah->hw_version.macVersion = AR_SREV_VERSION_9531; in ath9k_hw_read_revisions()
283 ah->hw_version.macVersion = AR_SREV_VERSION_9561; in ath9k_hw_read_revisions()
287 srev = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
290 ath_err(ath9k_hw_common(ah), in ath9k_hw_read_revisions()
299 ah->hw_version.macVersion = in ath9k_hw_read_revisions()
301 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
303 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_read_revisions()
304 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
306 ah->is_pciexpress = (val & in ath9k_hw_read_revisions()
309 if (!AR_SREV_9100(ah)) in ath9k_hw_read_revisions()
310 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); in ath9k_hw_read_revisions()
312 ah->hw_version.macRev = val & AR_SREV_REVISION; in ath9k_hw_read_revisions()
314 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) in ath9k_hw_read_revisions()
315 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
325 static void ath9k_hw_disablepcie(struct ath_hw *ah) in ath9k_hw_disablepcie() argument
327 if (!AR_SREV_5416(ah)) in ath9k_hw_disablepcie()
330 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
337 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
338 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
340 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
344 static bool ath9k_hw_chip_test(struct ath_hw *ah) in ath9k_hw_chip_test() argument
346 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_chip_test()
354 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_chip_test()
364 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
367 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
368 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
378 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
379 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
387 REG_WRITE(ah, regAddr[i], regHold[i]); in ath9k_hw_chip_test()
394 static void ath9k_hw_init_config(struct ath_hw *ah) in ath9k_hw_init_config() argument
396 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_config()
398 ah->config.dma_beacon_response_time = 1; in ath9k_hw_init_config()
399 ah->config.sw_beacon_response_time = 6; in ath9k_hw_init_config()
400 ah->config.cwm_ignore_extcca = false; in ath9k_hw_init_config()
401 ah->config.analog_shiftreg = 1; in ath9k_hw_init_config()
403 ah->config.rx_intr_mitigation = true; in ath9k_hw_init_config()
405 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_config()
406 ah->config.rimt_last = 500; in ath9k_hw_init_config()
407 ah->config.rimt_first = 2000; in ath9k_hw_init_config()
409 ah->config.rimt_last = 250; in ath9k_hw_init_config()
410 ah->config.rimt_first = 700; in ath9k_hw_init_config()
413 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_init_config()
414 ah->config.pll_pwrsave = 7; in ath9k_hw_init_config()
433 ah->config.serialize_regmode = SER_REG_MODE_AUTO; in ath9k_hw_init_config()
435 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { in ath9k_hw_init_config()
436 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || in ath9k_hw_init_config()
437 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && in ath9k_hw_init_config()
438 !ah->is_pciexpress)) { in ath9k_hw_init_config()
439 ah->config.serialize_regmode = SER_REG_MODE_ON; in ath9k_hw_init_config()
441 ah->config.serialize_regmode = SER_REG_MODE_OFF; in ath9k_hw_init_config()
446 ah->config.serialize_regmode); in ath9k_hw_init_config()
448 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_config()
449 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; in ath9k_hw_init_config()
451 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; in ath9k_hw_init_config()
454 static void ath9k_hw_init_defaults(struct ath_hw *ah) in ath9k_hw_init_defaults() argument
456 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_init_defaults()
461 ah->hw_version.magic = AR5416_MAGIC; in ath9k_hw_init_defaults()
462 ah->hw_version.subvendorid = 0; in ath9k_hw_init_defaults()
464 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | in ath9k_hw_init_defaults()
466 if (AR_SREV_9100(ah)) in ath9k_hw_init_defaults()
467 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; in ath9k_hw_init_defaults()
469 ah->slottime = 9; in ath9k_hw_init_defaults()
470 ah->globaltxtimeout = (u32) -1; in ath9k_hw_init_defaults()
471 ah->power_mode = ATH9K_PM_UNDEFINED; in ath9k_hw_init_defaults()
472 ah->htc_reset_init = true; in ath9k_hw_init_defaults()
474 ah->tpc_enabled = false; in ath9k_hw_init_defaults()
476 ah->ani_function = ATH9K_ANI_ALL; in ath9k_hw_init_defaults()
477 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_init_defaults()
478 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; in ath9k_hw_init_defaults()
480 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_defaults()
481 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
483 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
486 static void ath9k_hw_init_macaddr(struct ath_hw *ah) in ath9k_hw_init_macaddr() argument
488 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_macaddr()
498 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); in ath9k_hw_init_macaddr()
516 static int ath9k_hw_post_init(struct ath_hw *ah) in ath9k_hw_post_init() argument
518 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_post_init()
522 if (!ath9k_hw_chip_test(ah)) in ath9k_hw_post_init()
526 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
527 ecode = ar9002_hw_rf_claim(ah); in ath9k_hw_post_init()
532 ecode = ath9k_hw_eeprom_init(ah); in ath9k_hw_post_init()
536 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", in ath9k_hw_post_init()
537 ah->eep_ops->get_eeprom_ver(ah), in ath9k_hw_post_init()
538 ah->eep_ops->get_eeprom_rev(ah)); in ath9k_hw_post_init()
540 ath9k_hw_ani_init(ah); in ath9k_hw_post_init()
546 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
547 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_post_init()
549 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; in ath9k_hw_post_init()
550 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; in ath9k_hw_post_init()
557 static int ath9k_hw_attach_ops(struct ath_hw *ah) in ath9k_hw_attach_ops() argument
559 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_attach_ops()
560 return ar9002_hw_attach_ops(ah); in ath9k_hw_attach_ops()
562 ar9003_hw_attach_ops(ah); in ath9k_hw_attach_ops()
567 static int __ath9k_hw_init(struct ath_hw *ah) in __ath9k_hw_init() argument
569 struct ath_common *common = ath9k_hw_common(ah); in __ath9k_hw_init()
572 if (!ath9k_hw_read_revisions(ah)) { in __ath9k_hw_init()
577 switch (ah->hw_version.macVersion) { in __ath9k_hw_init()
599 ah->hw_version.macVersion, ah->hw_version.macRev); in __ath9k_hw_init()
608 if (AR_SREV_9300_20_OR_LATER(ah)) { in __ath9k_hw_init()
609 ah->WARegVal = REG_READ(ah, AR_WA); in __ath9k_hw_init()
610 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | in __ath9k_hw_init()
614 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in __ath9k_hw_init()
619 if (AR_SREV_9565(ah)) { in __ath9k_hw_init()
620 ah->WARegVal |= AR_WA_BIT22; in __ath9k_hw_init()
621 REG_WRITE(ah, AR_WA, ah->WARegVal); in __ath9k_hw_init()
624 ath9k_hw_init_defaults(ah); in __ath9k_hw_init()
625 ath9k_hw_init_config(ah); in __ath9k_hw_init()
627 r = ath9k_hw_attach_ops(ah); in __ath9k_hw_init()
631 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { in __ath9k_hw_init()
636 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || in __ath9k_hw_init()
637 AR_SREV_9330(ah) || AR_SREV_9550(ah)) in __ath9k_hw_init()
638 ah->is_pciexpress = false; in __ath9k_hw_init()
640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in __ath9k_hw_init()
641 ath9k_hw_init_cal_settings(ah); in __ath9k_hw_init()
643 if (!ah->is_pciexpress) in __ath9k_hw_init()
644 ath9k_hw_disablepcie(ah); in __ath9k_hw_init()
646 r = ath9k_hw_post_init(ah); in __ath9k_hw_init()
650 ath9k_hw_init_mode_gain_regs(ah); in __ath9k_hw_init()
651 r = ath9k_hw_fill_cap_info(ah); in __ath9k_hw_init()
655 ath9k_hw_init_macaddr(ah); in __ath9k_hw_init()
656 ath9k_hw_init_hang_checks(ah); in __ath9k_hw_init()
663 int ath9k_hw_init(struct ath_hw *ah) in ath9k_hw_init() argument
666 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init()
669 switch (ah->hw_version.devid) { in ath9k_hw_init()
696 ah->hw_version.devid); in ath9k_hw_init()
700 ret = __ath9k_hw_init(ah); in ath9k_hw_init()
708 ath_dynack_init(ah); in ath9k_hw_init()
714 static void ath9k_hw_init_qos(struct ath_hw *ah) in ath9k_hw_init_qos() argument
716 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_qos()
718 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
719 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
721 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
726 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ath9k_hw_init_qos()
727 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
728 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
729 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
730 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
732 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_qos()
735 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) in ar9003_get_pll_sqsum_dvc() argument
737 struct ath_common *common = ath9k_hw_common(ah); in ar9003_get_pll_sqsum_dvc()
740 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
742 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
744 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
756 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; in ar9003_get_pll_sqsum_dvc()
760 static void ath9k_hw_init_pll(struct ath_hw *ah, in ath9k_hw_init_pll() argument
765 pll = ath9k_hw_compute_pll_control(ah, chan); in ath9k_hw_init_pll()
767 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_init_pll()
769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
771 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
773 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
778 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
783 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
785 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
787 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
791 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
794 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
797 } else if (AR_SREV_9330(ah)) { in ath9k_hw_init_pll()
800 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
811 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); in ath9k_hw_init_pll()
814 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, in ath9k_hw_init_pll()
817 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
822 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); in ath9k_hw_init_pll()
825 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); in ath9k_hw_init_pll()
826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); in ath9k_hw_init_pll()
829 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
831 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_pll()
832 AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
835 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
839 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); in ath9k_hw_init_pll()
842 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
843 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
853 if (AR_SREV_9340(ah)) { in ath9k_hw_init_pll()
859 pll2_divfrac = (AR_SREV_9531(ah) || in ath9k_hw_init_pll()
860 AR_SREV_9561(ah)) ? in ath9k_hw_init_pll()
866 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
867 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ath9k_hw_init_pll()
871 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
874 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
878 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
879 if (AR_SREV_9340(ah)) in ath9k_hw_init_pll()
885 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
892 if (AR_SREV_9531(ah)) in ath9k_hw_init_pll()
900 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
902 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ath9k_hw_init_pll()
903 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
904 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); in ath9k_hw_init_pll()
906 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
907 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); in ath9k_hw_init_pll()
912 if (AR_SREV_9565(ah)) in ath9k_hw_init_pll()
914 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ath9k_hw_init_pll()
916 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ath9k_hw_init_pll()
917 AR_SREV_9550(ah)) in ath9k_hw_init_pll()
921 if (AR_SREV_9271(ah)) { in ath9k_hw_init_pll()
923 REG_WRITE(ah, 0x50040, 0x304); in ath9k_hw_init_pll()
928 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); in ath9k_hw_init_pll()
931 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, in ath9k_hw_init_interrupt_masks() argument
942 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_interrupt_masks()
943 AR_SREV_9561(ah)) in ath9k_hw_init_interrupt_masks()
946 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
948 if (ah->config.rx_intr_mitigation) { in ath9k_hw_init_interrupt_masks()
956 if (ah->config.rx_intr_mitigation) { in ath9k_hw_init_interrupt_masks()
965 if (ah->config.tx_intr_mitigation) { in ath9k_hw_init_interrupt_masks()
973 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_interrupt_masks()
975 REG_WRITE(ah, AR_IMR, imr_reg); in ath9k_hw_init_interrupt_masks()
976 ah->imrs2_reg |= AR_IMR_S2_GTT; in ath9k_hw_init_interrupt_masks()
977 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_init_interrupt_masks()
979 if (ah->msi_enabled) { in ath9k_hw_init_interrupt_masks()
980 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI); in ath9k_hw_init_interrupt_masks()
981 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN; in ath9k_hw_init_interrupt_masks()
982 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; in ath9k_hw_init_interrupt_masks()
983 REG_WRITE(ah, AR_INTCFG, msi_cfg); in ath9k_hw_init_interrupt_masks()
984 ath_dbg(ath9k_hw_common(ah), ANY, in ath9k_hw_init_interrupt_masks()
986 REG_READ(ah, AR_INTCFG), msi_cfg); in ath9k_hw_init_interrupt_masks()
989 if (!AR_SREV_9100(ah)) { in ath9k_hw_init_interrupt_masks()
990 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
991 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); in ath9k_hw_init_interrupt_masks()
992 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
995 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_interrupt_masks()
997 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
998 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
999 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
1000 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
1001 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
1005 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) in ath9k_hw_set_sifs_time() argument
1007 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); in ath9k_hw_set_sifs_time()
1009 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); in ath9k_hw_set_sifs_time()
1012 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) in ath9k_hw_setslottime() argument
1014 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_setslottime()
1016 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); in ath9k_hw_setslottime()
1019 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_ack_timeout() argument
1021 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_ack_timeout()
1023 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); in ath9k_hw_set_ack_timeout()
1026 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_cts_timeout() argument
1028 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_cts_timeout()
1030 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); in ath9k_hw_set_cts_timeout()
1033 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) in ath9k_hw_set_global_txtimeout() argument
1036 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", in ath9k_hw_set_global_txtimeout()
1038 ah->globaltxtimeout = (u32) -1; in ath9k_hw_set_global_txtimeout()
1041 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); in ath9k_hw_set_global_txtimeout()
1042 ah->globaltxtimeout = tu; in ath9k_hw_set_global_txtimeout()
1047 void ath9k_hw_init_global_settings(struct ath_hw *ah) in ath9k_hw_init_global_settings() argument
1049 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_global_settings()
1050 const struct ath9k_channel *chan = ah->curchan; in ath9k_hw_init_global_settings()
1057 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", in ath9k_hw_init_global_settings()
1058 ah->misc_mode); in ath9k_hw_init_global_settings()
1063 if (ah->misc_mode != 0) in ath9k_hw_init_global_settings()
1064 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); in ath9k_hw_init_global_settings()
1066 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1092 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1100 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_init_global_settings()
1104 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ in ath9k_hw_init_global_settings()
1106 reg = REG_READ(ah, AR_USEC); in ath9k_hw_init_global_settings()
1111 slottime = ah->slottime; in ath9k_hw_init_global_settings()
1115 slottime += 3 * ah->coverage_class; in ath9k_hw_init_global_settings()
1128 acktimeout += 64 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1129 ctstimeout += 48 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1132 if (ah->dynack.enabled) { in ath9k_hw_init_global_settings()
1133 acktimeout = ah->dynack.ackto; in ath9k_hw_init_global_settings()
1137 ah->dynack.ackto = acktimeout; in ath9k_hw_init_global_settings()
1140 ath9k_hw_set_sifs_time(ah, sifstime); in ath9k_hw_init_global_settings()
1141 ath9k_hw_setslottime(ah, slottime); in ath9k_hw_init_global_settings()
1142 ath9k_hw_set_ack_timeout(ah, acktimeout); in ath9k_hw_init_global_settings()
1143 ath9k_hw_set_cts_timeout(ah, ctstimeout); in ath9k_hw_init_global_settings()
1144 if (ah->globaltxtimeout != (u32) -1) in ath9k_hw_init_global_settings()
1145 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); in ath9k_hw_init_global_settings()
1147 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); in ath9k_hw_init_global_settings()
1148 REG_RMW(ah, AR_USEC, in ath9k_hw_init_global_settings()
1155 REG_RMW(ah, AR_TXSIFS, in ath9k_hw_init_global_settings()
1161 void ath9k_hw_deinit(struct ath_hw *ah) in ath9k_hw_deinit() argument
1163 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_deinit()
1168 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); in ath9k_hw_deinit()
1192 static inline void ath9k_hw_set_dma(struct ath_hw *ah) in ath9k_hw_set_dma() argument
1194 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_dma()
1197 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1202 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1203 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1208 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1210 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1217 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1218 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); in ath9k_hw_set_dma()
1220 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1225 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1230 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1232 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_dma()
1233 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); in ath9k_hw_set_dma()
1234 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); in ath9k_hw_set_dma()
1236 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - in ath9k_hw_set_dma()
1237 ah->caps.rx_status_len); in ath9k_hw_set_dma()
1244 if (AR_SREV_9285(ah)) { in ath9k_hw_set_dma()
1250 } else if (AR_SREV_9340_13_OR_LATER(ah)) { in ath9k_hw_set_dma()
1257 if (!AR_SREV_9271(ah)) in ath9k_hw_set_dma()
1258 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); in ath9k_hw_set_dma()
1260 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1262 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1263 ath9k_hw_reset_txstatus_ring(ah); in ath9k_hw_set_dma()
1266 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) in ath9k_hw_set_operating_mode() argument
1271 ENABLE_REG_RMW_BUFFER(ah); in ath9k_hw_set_operating_mode()
1274 if (!AR_SREV_9340_13(ah)) { in ath9k_hw_set_operating_mode()
1276 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1286 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1289 if (!ah->is_monitoring) in ath9k_hw_set_operating_mode()
1293 REG_RMW(ah, AR_STA_ID1, set, mask); in ath9k_hw_set_operating_mode()
1294 REG_RMW_BUFFER_FLUSH(ah); in ath9k_hw_set_operating_mode()
1297 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, in ath9k_hw_get_delta_slope_vals() argument
1319 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) in ath9k_hw_ar9330_reset_war() argument
1324 npend = ath9k_hw_numtxpending(ah, i); in ath9k_hw_ar9330_reset_war()
1329 if (ah->external_reset && in ath9k_hw_ar9330_reset_war()
1333 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_ar9330_reset_war()
1336 reset_err = ah->external_reset(); in ath9k_hw_ar9330_reset_war()
1338 ath_err(ath9k_hw_common(ah), in ath9k_hw_ar9330_reset_war()
1344 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_ar9330_reset_war()
1350 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) in ath9k_hw_set_reset() argument
1355 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1356 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, in ath9k_hw_set_reset()
1358 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); in ath9k_hw_set_reset()
1361 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset()
1363 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset()
1364 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset()
1368 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset()
1371 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1375 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); in ath9k_hw_set_reset()
1376 if (AR_SREV_9340(ah)) in ath9k_hw_set_reset()
1384 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_set_reset()
1387 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1389 REG_WRITE(ah, AR_RC, val); in ath9k_hw_set_reset()
1391 } else if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1392 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset()
1399 if (AR_SREV_9330(ah)) { in ath9k_hw_set_reset()
1400 if (!ath9k_hw_ar9330_reset_war(ah, type)) in ath9k_hw_set_reset()
1404 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_reset()
1405 ar9003_mci_check_gpm_offset(ah); in ath9k_hw_set_reset()
1410 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) { in ath9k_hw_set_reset()
1411 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset()
1412 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK, in ath9k_hw_set_reset()
1414 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset()
1417 REG_WRITE(ah, AR_RTC_RC, rst_flags); in ath9k_hw_set_reset()
1419 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset()
1421 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1423 else if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1428 REG_WRITE(ah, AR_RTC_RC, 0); in ath9k_hw_set_reset()
1429 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_reset()
1430 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); in ath9k_hw_set_reset()
1434 if (!AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1435 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1437 if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1443 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) in ath9k_hw_set_reset_power_on() argument
1445 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset_power_on()
1447 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_power_on()
1448 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_power_on()
1452 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset_power_on()
1455 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1456 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset_power_on()
1458 REG_WRITE(ah, AR_RTC_RESET, 0); in ath9k_hw_set_reset_power_on()
1460 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset_power_on()
1464 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1465 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1467 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_set_reset_power_on()
1469 if (!ath9k_hw_wait(ah, in ath9k_hw_set_reset_power_on()
1474 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); in ath9k_hw_set_reset_power_on()
1478 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); in ath9k_hw_set_reset_power_on()
1481 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) in ath9k_hw_set_reset_reg() argument
1485 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_reg()
1486 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_reg()
1490 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_reset_reg()
1493 if (!ah->reset_power_on) in ath9k_hw_set_reset_reg()
1498 ret = ath9k_hw_set_reset_power_on(ah); in ath9k_hw_set_reset_reg()
1500 ah->reset_power_on = true; in ath9k_hw_set_reset_reg()
1504 ret = ath9k_hw_set_reset(ah, type); in ath9k_hw_set_reset_reg()
1513 static bool ath9k_hw_chip_reset(struct ath_hw *ah, in ath9k_hw_chip_reset() argument
1518 if (AR_SREV_9280(ah)) { in ath9k_hw_chip_reset()
1519 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) in ath9k_hw_chip_reset()
1523 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || in ath9k_hw_chip_reset()
1524 (REG_READ(ah, AR_CR) & AR_CR_RXE)) in ath9k_hw_chip_reset()
1527 if (!ath9k_hw_set_reset_reg(ah, reset_type)) in ath9k_hw_chip_reset()
1530 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_chip_reset()
1533 ah->chip_fullsleep = false; in ath9k_hw_chip_reset()
1535 if (AR_SREV_9330(ah)) in ath9k_hw_chip_reset()
1536 ar9003_hw_internal_regulator_apply(ah); in ath9k_hw_chip_reset()
1537 ath9k_hw_init_pll(ah, chan); in ath9k_hw_chip_reset()
1542 static bool ath9k_hw_channel_change(struct ath_hw *ah, in ath9k_hw_channel_change() argument
1545 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_channel_change()
1546 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_channel_change()
1553 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; in ath9k_hw_channel_change()
1559 if (ath9k_hw_numtxpending(ah, qnum)) { in ath9k_hw_channel_change()
1566 if (!ath9k_hw_rfbus_req(ah)) { in ath9k_hw_channel_change()
1572 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_channel_change()
1576 ath9k_hw_init_pll(ah, chan); in ath9k_hw_channel_change()
1578 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { in ath9k_hw_channel_change()
1584 ath9k_hw_set_channel_regs(ah, chan); in ath9k_hw_channel_change()
1586 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_channel_change()
1591 ath9k_hw_set_clockrate(ah); in ath9k_hw_channel_change()
1592 ath9k_hw_apply_txpower(ah, chan, false); in ath9k_hw_channel_change()
1594 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_channel_change()
1595 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_channel_change()
1598 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_channel_change()
1600 ath9k_hw_init_bb(ah, chan); in ath9k_hw_channel_change()
1601 ath9k_hw_rfbus_done(ah); in ath9k_hw_channel_change()
1604 ah->ah_flags |= AH_FASTCC; in ath9k_hw_channel_change()
1605 ath9k_hw_init_cal(ah, chan); in ath9k_hw_channel_change()
1606 ah->ah_flags &= ~AH_FASTCC; in ath9k_hw_channel_change()
1612 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) in ath9k_hw_apply_gpio_override() argument
1614 u32 gpio_mask = ah->gpio_mask; in ath9k_hw_apply_gpio_override()
1621 ath9k_hw_gpio_request_out(ah, i, NULL, in ath9k_hw_apply_gpio_override()
1623 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); in ath9k_hw_apply_gpio_override()
1627 void ath9k_hw_check_nav(struct ath_hw *ah) in ath9k_hw_check_nav() argument
1629 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_check_nav()
1632 val = REG_READ(ah, AR_NAV); in ath9k_hw_check_nav()
1635 REG_WRITE(ah, AR_NAV, 0); in ath9k_hw_check_nav()
1640 bool ath9k_hw_check_alive(struct ath_hw *ah) in ath9k_hw_check_alive() argument
1646 if (REG_READ(ah, AR_CFG) == 0xdeadbeef) in ath9k_hw_check_alive()
1649 if (AR_SREV_9300(ah)) in ath9k_hw_check_alive()
1650 return !ath9k_hw_detect_mac_hang(ah); in ath9k_hw_check_alive()
1652 if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_check_alive()
1655 last_val = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1657 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1680 static void ath9k_hw_init_mfp(struct ath_hw *ah) in ath9k_hw_init_mfp() argument
1683 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1686 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, in ath9k_hw_init_mfp()
1688 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) in ath9k_hw_init_mfp()
1689 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1691 ah->sw_mgmt_crypto_tx = false; in ath9k_hw_init_mfp()
1692 ah->sw_mgmt_crypto_rx = false; in ath9k_hw_init_mfp()
1693 } else if (AR_SREV_9160_10_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1695 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1697 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1699 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1700 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1702 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1703 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1707 static void ath9k_hw_reset_opmode(struct ath_hw *ah, in ath9k_hw_reset_opmode() argument
1710 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset_opmode()
1712 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset_opmode()
1714 REG_RMW(ah, AR_STA_ID1, macStaId1 in ath9k_hw_reset_opmode()
1716 | ah->sta_id1_defaults, in ath9k_hw_reset_opmode()
1719 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ath9k_hw_reset_opmode()
1720 ath9k_hw_write_associd(ah); in ath9k_hw_reset_opmode()
1721 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset_opmode()
1722 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_reset_opmode()
1724 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset_opmode()
1726 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_reset_opmode()
1729 static void ath9k_hw_init_queues(struct ath_hw *ah) in ath9k_hw_init_queues() argument
1733 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_queues()
1736 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ath9k_hw_init_queues()
1738 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_queues()
1740 ah->intr_txqs = 0; in ath9k_hw_init_queues()
1742 ath9k_hw_resettxqueue(ah, i); in ath9k_hw_init_queues()
1748 static void ath9k_hw_init_desc(struct ath_hw *ah) in ath9k_hw_init_desc() argument
1750 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_desc()
1752 if (AR_SREV_9100(ah)) { in ath9k_hw_init_desc()
1754 mask = REG_READ(ah, AR_CFG); in ath9k_hw_init_desc()
1760 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_init_desc()
1762 REG_READ(ah, AR_CFG)); in ath9k_hw_init_desc()
1767 if (AR_SREV_9271(ah)) in ath9k_hw_init_desc()
1768 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in ath9k_hw_init_desc()
1770 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1773 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || in ath9k_hw_init_desc()
1774 AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_desc()
1775 AR_SREV_9561(ah)) in ath9k_hw_init_desc()
1776 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); in ath9k_hw_init_desc()
1778 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1787 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_do_fastcc() argument
1789 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_do_fastcc()
1790 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_do_fastcc()
1793 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) in ath9k_hw_do_fastcc()
1796 if (ah->chip_fullsleep) in ath9k_hw_do_fastcc()
1799 if (!ah->curchan) in ath9k_hw_do_fastcc()
1802 if (chan->channel == ah->curchan->channel) in ath9k_hw_do_fastcc()
1805 if ((ah->curchan->channelFlags | chan->channelFlags) & in ath9k_hw_do_fastcc()
1813 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) in ath9k_hw_do_fastcc()
1816 if (!ath9k_hw_check_alive(ah)) in ath9k_hw_do_fastcc()
1823 if (AR_SREV_9462(ah) && (ah->caldata && in ath9k_hw_do_fastcc()
1824 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1825 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1826 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) in ath9k_hw_do_fastcc()
1830 ah->curchan->channel, chan->channel); in ath9k_hw_do_fastcc()
1832 ret = ath9k_hw_channel_change(ah, chan); in ath9k_hw_do_fastcc()
1836 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_do_fastcc()
1837 ar9003_mci_2g5g_switch(ah, false); in ath9k_hw_do_fastcc()
1839 ath9k_hw_loadnf(ah, ah->curchan); in ath9k_hw_do_fastcc()
1840 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_do_fastcc()
1842 if (AR_SREV_9271(ah)) in ath9k_hw_do_fastcc()
1843 ar9002_hw_load_ani_reg(ah, chan); in ath9k_hw_do_fastcc()
1867 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_reset() argument
1870 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset()
1879 bool save_fullsleep = ah->chip_fullsleep; in ath9k_hw_reset()
1881 if (ath9k_hw_mci_is_enabled(ah)) { in ath9k_hw_reset()
1882 start_mci_reset = ar9003_mci_start_reset(ah, chan); in ath9k_hw_reset()
1887 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_reset()
1890 if (ah->curchan && !ah->chip_fullsleep) in ath9k_hw_reset()
1891 ath9k_hw_getnf(ah, ah->curchan); in ath9k_hw_reset()
1893 ah->caldata = caldata; in ath9k_hw_reset()
1898 ath9k_init_nfcal_hist_buffer(ah, chan); in ath9k_hw_reset()
1902 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); in ath9k_hw_reset()
1905 r = ath9k_hw_do_fastcc(ah, chan); in ath9k_hw_reset()
1910 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1911 ar9003_mci_stop_bt(ah, save_fullsleep); in ath9k_hw_reset()
1913 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); in ath9k_hw_reset()
1917 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; in ath9k_hw_reset()
1921 tsf = ath9k_hw_gettsf64(ah); in ath9k_hw_reset()
1923 saveLedState = REG_READ(ah, AR_CFG_LED) & in ath9k_hw_reset()
1927 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_reset()
1929 ah->paprd_table_write_done = false; in ath9k_hw_reset()
1932 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1933 REG_WRITE(ah, in ath9k_hw_reset()
1939 if (!ath9k_hw_chip_reset(ah, chan)) { in ath9k_hw_reset()
1945 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1946 ah->htc_reset_init = false; in ath9k_hw_reset()
1947 REG_WRITE(ah, in ath9k_hw_reset()
1955 ath9k_hw_settsf64(ah, tsf + tsf_offset); in ath9k_hw_reset()
1957 if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_reset()
1958 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ath9k_hw_reset()
1960 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
1961 ar9002_hw_enable_async_fifo(ah); in ath9k_hw_reset()
1963 r = ath9k_hw_process_ini(ah, chan); in ath9k_hw_reset()
1967 ath9k_hw_set_rfmode(ah, chan); in ath9k_hw_reset()
1969 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1970 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); in ath9k_hw_reset()
1977 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { in ath9k_hw_reset()
1979 ath9k_hw_settsf64(ah, tsf + tsf_offset); in ath9k_hw_reset()
1982 ath9k_hw_init_mfp(ah); in ath9k_hw_reset()
1984 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_reset()
1985 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_reset()
1986 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_reset()
1988 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); in ath9k_hw_reset()
1990 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_reset()
1994 ath9k_hw_set_clockrate(ah); in ath9k_hw_reset()
1996 ath9k_hw_init_queues(ah); in ath9k_hw_reset()
1997 ath9k_hw_init_interrupt_masks(ah, ah->opmode); in ath9k_hw_reset()
1998 ath9k_hw_ani_cache_ini_regs(ah); in ath9k_hw_reset()
1999 ath9k_hw_init_qos(ah); in ath9k_hw_reset()
2001 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_hw_reset()
2002 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill"); in ath9k_hw_reset()
2004 ath9k_hw_init_global_settings(ah); in ath9k_hw_reset()
2006 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_reset()
2007 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, in ath9k_hw_reset()
2009 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, in ath9k_hw_reset()
2011 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
2015 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_reset()
2017 ath9k_hw_set_dma(ah); in ath9k_hw_reset()
2019 if (!ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
2020 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
2022 ENABLE_REG_RMW_BUFFER(ah); in ath9k_hw_reset()
2023 if (ah->config.rx_intr_mitigation) { in ath9k_hw_reset()
2024 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); in ath9k_hw_reset()
2025 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); in ath9k_hw_reset()
2028 if (ah->config.tx_intr_mitigation) { in ath9k_hw_reset()
2029 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); in ath9k_hw_reset()
2030 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); in ath9k_hw_reset()
2032 REG_RMW_BUFFER_FLUSH(ah); in ath9k_hw_reset()
2034 ath9k_hw_init_bb(ah, chan); in ath9k_hw_reset()
2040 if (!ath9k_hw_init_cal(ah, chan)) in ath9k_hw_reset()
2043 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) in ath9k_hw_reset()
2046 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset()
2048 ath9k_hw_restore_chainmask(ah); in ath9k_hw_reset()
2049 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); in ath9k_hw_reset()
2051 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset()
2053 ath9k_hw_gen_timer_start_tsf2(ah); in ath9k_hw_reset()
2055 ath9k_hw_init_desc(ah); in ath9k_hw_reset()
2057 if (ath9k_hw_btcoex_is_enabled(ah)) in ath9k_hw_reset()
2058 ath9k_hw_btcoex_enable(ah); in ath9k_hw_reset()
2060 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
2061 ar9003_mci_check_bt(ah); in ath9k_hw_reset()
2063 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_reset()
2064 ath9k_hw_loadnf(ah, chan); in ath9k_hw_reset()
2065 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_reset()
2068 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
2069 ar9003_hw_bb_watchdog_config(ah); in ath9k_hw_reset()
2071 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) in ath9k_hw_reset()
2072 ar9003_hw_disable_phy_restart(ah); in ath9k_hw_reset()
2074 ath9k_hw_apply_gpio_override(ah); in ath9k_hw_reset()
2076 if (AR_SREV_9565(ah) && common->bt_ant_diversity) in ath9k_hw_reset()
2077 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); in ath9k_hw_reset()
2079 if (ah->hw->conf.radar_enabled) { in ath9k_hw_reset()
2081 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); in ath9k_hw_reset()
2082 ath9k_hw_set_radar_params(ah); in ath9k_hw_reset()
2097 static void ath9k_set_power_sleep(struct ath_hw *ah) in ath9k_set_power_sleep() argument
2099 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_sleep()
2101 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_set_power_sleep()
2102 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2103 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2104 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep()
2106 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); in ath9k_set_power_sleep()
2114 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep()
2116 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_sleep()
2119 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
2120 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_set_power_sleep()
2123 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { in ath9k_set_power_sleep()
2124 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); in ath9k_set_power_sleep()
2129 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
2130 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()
2138 static void ath9k_set_power_network_sleep(struct ath_hw *ah) in ath9k_set_power_network_sleep() argument
2140 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_set_power_network_sleep()
2142 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_network_sleep()
2146 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
2159 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2160 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, in ath9k_set_power_network_sleep()
2166 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_network_sleep()
2168 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2173 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_network_sleep()
2174 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
2177 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) in ath9k_hw_set_power_awake() argument
2183 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_power_awake()
2184 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_power_awake()
2188 if ((REG_READ(ah, AR_RTC_STATUS) & in ath9k_hw_set_power_awake()
2190 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in ath9k_hw_set_power_awake()
2193 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_power_awake()
2194 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_set_power_awake()
2196 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2197 REG_SET_BIT(ah, AR_RTC_RESET, in ath9k_hw_set_power_awake()
2200 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2202 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2208 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; in ath9k_hw_set_power_awake()
2212 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2216 ath_err(ath9k_hw_common(ah), in ath9k_hw_set_power_awake()
2222 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_power_awake()
2223 ar9003_mci_set_power_awake(ah); in ath9k_hw_set_power_awake()
2225 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake()
2230 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) in ath9k_hw_setpower() argument
2232 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_setpower()
2241 if (ah->power_mode == mode) in ath9k_hw_setpower()
2245 modes[ah->power_mode], modes[mode]); in ath9k_hw_setpower()
2249 status = ath9k_hw_set_power_awake(ah); in ath9k_hw_setpower()
2252 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_setpower()
2253 ar9003_mci_set_full_sleep(ah); in ath9k_hw_setpower()
2255 ath9k_set_power_sleep(ah); in ath9k_hw_setpower()
2256 ah->chip_fullsleep = true; in ath9k_hw_setpower()
2259 ath9k_set_power_network_sleep(ah); in ath9k_hw_setpower()
2265 ah->power_mode = mode; in ath9k_hw_setpower()
2273 if (!(ah->ah_flags & AH_UNPLUGGED)) in ath9k_hw_setpower()
2284 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) in ath9k_hw_beaconinit() argument
2288 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_beaconinit()
2290 switch (ah->opmode) { in ath9k_hw_beaconinit()
2292 REG_SET_BIT(ah, AR_TXCFG, in ath9k_hw_beaconinit()
2297 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); in ath9k_hw_beaconinit()
2298 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - in ath9k_hw_beaconinit()
2299 TU_TO_USEC(ah->config.dma_beacon_response_time)); in ath9k_hw_beaconinit()
2300 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - in ath9k_hw_beaconinit()
2301 TU_TO_USEC(ah->config.sw_beacon_response_time)); in ath9k_hw_beaconinit()
2306 ath_dbg(ath9k_hw_common(ah), BEACON, in ath9k_hw_beaconinit()
2307 "%s: unsupported opmode: %d\n", __func__, ah->opmode); in ath9k_hw_beaconinit()
2311 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2312 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2313 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2315 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_beaconinit()
2317 REG_SET_BIT(ah, AR_TIMER_MODE, flags); in ath9k_hw_beaconinit()
2321 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, in ath9k_hw_set_sta_beacon_timers() argument
2325 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_set_sta_beacon_timers()
2326 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_sta_beacon_timers()
2328 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2330 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); in ath9k_hw_set_sta_beacon_timers()
2331 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2332 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2334 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2336 REG_RMW_FIELD(ah, AR_RSSI_THR, in ath9k_hw_set_sta_beacon_timers()
2358 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2360 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2361 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2363 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
2372 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
2375 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); in ath9k_hw_set_sta_beacon_timers()
2376 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); in ath9k_hw_set_sta_beacon_timers()
2378 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2380 REG_SET_BIT(ah, AR_TIMER_MODE, in ath9k_hw_set_sta_beacon_timers()
2385 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
2415 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) in ath9k_hw_dfs_tested() argument
2418 switch (ah->hw_version.macVersion) { in ath9k_hw_dfs_tested()
2429 static void ath9k_gpio_cap_init(struct ath_hw *ah) in ath9k_gpio_cap_init() argument
2431 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_gpio_cap_init()
2433 if (AR_SREV_9271(ah)) { in ath9k_gpio_cap_init()
2436 } else if (AR_DEVID_7010(ah)) { in ath9k_gpio_cap_init()
2439 } else if (AR_SREV_9287(ah)) { in ath9k_gpio_cap_init()
2442 } else if (AR_SREV_9285(ah)) { in ath9k_gpio_cap_init()
2445 } else if (AR_SREV_9280(ah)) { in ath9k_gpio_cap_init()
2448 } else if (AR_SREV_9300(ah)) { in ath9k_gpio_cap_init()
2451 } else if (AR_SREV_9330(ah)) { in ath9k_gpio_cap_init()
2454 } else if (AR_SREV_9340(ah)) { in ath9k_gpio_cap_init()
2457 } else if (AR_SREV_9462(ah)) { in ath9k_gpio_cap_init()
2460 } else if (AR_SREV_9485(ah)) { in ath9k_gpio_cap_init()
2463 } else if (AR_SREV_9531(ah)) { in ath9k_gpio_cap_init()
2466 } else if (AR_SREV_9550(ah)) { in ath9k_gpio_cap_init()
2469 } else if (AR_SREV_9561(ah)) { in ath9k_gpio_cap_init()
2472 } else if (AR_SREV_9565(ah)) { in ath9k_gpio_cap_init()
2475 } else if (AR_SREV_9580(ah)) { in ath9k_gpio_cap_init()
2484 int ath9k_hw_fill_cap_info(struct ath_hw *ah) in ath9k_hw_fill_cap_info() argument
2486 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_fill_cap_info()
2487 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_fill_cap_info()
2488 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_fill_cap_info()
2493 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_fill_cap_info()
2496 if (ah->opmode != NL80211_IFTYPE_AP && in ath9k_hw_fill_cap_info()
2497 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { in ath9k_hw_fill_cap_info()
2507 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); in ath9k_hw_fill_cap_info()
2510 if (ah->disable_5ghz) in ath9k_hw_fill_cap_info()
2517 if (ah->disable_2ghz) in ath9k_hw_fill_cap_info()
2528 ath9k_gpio_cap_init(ah); in ath9k_hw_fill_cap_info()
2530 if (AR_SREV_9485(ah) || in ath9k_hw_fill_cap_info()
2531 AR_SREV_9285(ah) || in ath9k_hw_fill_cap_info()
2532 AR_SREV_9330(ah) || in ath9k_hw_fill_cap_info()
2533 AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2535 else if (!AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2537 else if (!AR_SREV_9300_20_OR_LATER(ah) || in ath9k_hw_fill_cap_info()
2538 AR_SREV_9340(ah) || in ath9k_hw_fill_cap_info()
2539 AR_SREV_9462(ah) || in ath9k_hw_fill_cap_info()
2540 AR_SREV_9531(ah)) in ath9k_hw_fill_cap_info()
2545 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); in ath9k_hw_fill_cap_info()
2550 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && in ath9k_hw_fill_cap_info()
2552 !(AR_SREV_9271(ah))) in ath9k_hw_fill_cap_info()
2554 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; in ath9k_hw_fill_cap_info()
2555 else if (AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2559 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); in ath9k_hw_fill_cap_info()
2563 ah->txchainmask = pCap->tx_chainmask; in ath9k_hw_fill_cap_info()
2564 ah->rxchainmask = pCap->rx_chainmask; in ath9k_hw_fill_cap_info()
2566 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; in ath9k_hw_fill_cap_info()
2569 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2570 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; in ath9k_hw_fill_cap_info()
2574 if (ah->hw_version.devid != AR2427_DEVID_PCIE) in ath9k_hw_fill_cap_info()
2579 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2585 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); in ath9k_hw_fill_cap_info()
2586 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { in ath9k_hw_fill_cap_info()
2587 ah->rfkill_gpio = in ath9k_hw_fill_cap_info()
2588 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); in ath9k_hw_fill_cap_info()
2589 ah->rfkill_polarity = in ath9k_hw_fill_cap_info()
2590 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); in ath9k_hw_fill_cap_info()
2595 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2600 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) in ath9k_hw_fill_cap_info()
2605 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2607 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && in ath9k_hw_fill_cap_info()
2608 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2618 if (AR_SREV_9280_20(ah)) in ath9k_hw_fill_cap_info()
2622 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2625 if (AR_SREV_9561(ah)) in ath9k_hw_fill_cap_info()
2626 ah->ent_mode = 0x3BDA000; in ath9k_hw_fill_cap_info()
2627 else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2628 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); in ath9k_hw_fill_cap_info()
2630 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) in ath9k_hw_fill_cap_info()
2633 if (AR_SREV_9285(ah)) { in ath9k_hw_fill_cap_info()
2634 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { in ath9k_hw_fill_cap_info()
2636 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2644 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2645 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) in ath9k_hw_fill_cap_info()
2649 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2650 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2657 if (ath9k_hw_dfs_tested(ah)) in ath9k_hw_fill_cap_info()
2672 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2673 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) in ath9k_hw_fill_cap_info()
2676 if (AR_SREV_9462_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2680 if (AR_SREV_9300_20_OR_LATER(ah) && in ath9k_hw_fill_cap_info()
2681 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) in ath9k_hw_fill_cap_info()
2685 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2686 ah->wow.max_patterns = MAX_NUM_PATTERN; in ath9k_hw_fill_cap_info()
2688 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; in ath9k_hw_fill_cap_info()
2698 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type) in ath9k_hw_gpio_cfg_output_mux() argument
2712 if (AR_SREV_9280_20_OR_LATER(ah) || in ath9k_hw_gpio_cfg_output_mux()
2714 REG_RMW(ah, addr, (type << gpio_shift), in ath9k_hw_gpio_cfg_output_mux()
2717 tmp = REG_READ(ah, addr); in ath9k_hw_gpio_cfg_output_mux()
2721 REG_WRITE(ah, addr, tmp); in ath9k_hw_gpio_cfg_output_mux()
2727 static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out, in ath9k_hw_gpio_cfg_soc() argument
2732 if (ah->caps.gpio_requested & BIT(gpio)) in ath9k_hw_gpio_cfg_soc()
2737 ath_err(ath9k_hw_common(ah), "request GPIO%d failed:%d\n", in ath9k_hw_gpio_cfg_soc()
2742 ah->caps.gpio_requested |= BIT(gpio); in ath9k_hw_gpio_cfg_soc()
2745 static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out, in ath9k_hw_gpio_cfg_wmac() argument
2750 if (AR_DEVID_7010(ah)) { in ath9k_hw_gpio_cfg_wmac()
2753 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift, in ath9k_hw_gpio_cfg_wmac()
2755 } else if (AR_SREV_SOC(ah)) { in ath9k_hw_gpio_cfg_wmac()
2757 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, in ath9k_hw_gpio_cfg_wmac()
2763 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, in ath9k_hw_gpio_cfg_wmac()
2767 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); in ath9k_hw_gpio_cfg_wmac()
2771 static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out, in ath9k_hw_gpio_request() argument
2774 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_gpio_request()
2776 if (BIT(gpio) & ah->caps.gpio_mask) in ath9k_hw_gpio_request()
2777 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type); in ath9k_hw_gpio_request()
2778 else if (AR_SREV_SOC(ah)) in ath9k_hw_gpio_request()
2779 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label); in ath9k_hw_gpio_request()
2784 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label) in ath9k_hw_gpio_request_in() argument
2786 ath9k_hw_gpio_request(ah, gpio, false, label, 0); in ath9k_hw_gpio_request_in()
2790 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label, in ath9k_hw_gpio_request_out() argument
2793 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type); in ath9k_hw_gpio_request_out()
2797 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio) in ath9k_hw_gpio_free() argument
2799 if (!AR_SREV_SOC(ah)) in ath9k_hw_gpio_free()
2802 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_gpio_free()
2804 if (ah->caps.gpio_requested & BIT(gpio)) { in ath9k_hw_gpio_free()
2806 ah->caps.gpio_requested &= ~BIT(gpio); in ath9k_hw_gpio_free()
2811 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) in ath9k_hw_gpio_get() argument
2816 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y)) in ath9k_hw_gpio_get()
2818 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_gpio_get()
2820 if (BIT(gpio) & ah->caps.gpio_mask) { in ath9k_hw_gpio_get()
2821 if (AR_SREV_9271(ah)) in ath9k_hw_gpio_get()
2823 else if (AR_SREV_9287(ah)) in ath9k_hw_gpio_get()
2825 else if (AR_SREV_9285(ah)) in ath9k_hw_gpio_get()
2827 else if (AR_SREV_9280(ah)) in ath9k_hw_gpio_get()
2829 else if (AR_DEVID_7010(ah)) in ath9k_hw_gpio_get()
2830 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio); in ath9k_hw_gpio_get()
2831 else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_gpio_get()
2832 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio); in ath9k_hw_gpio_get()
2835 } else if (BIT(gpio) & ah->caps.gpio_requested) { in ath9k_hw_gpio_get()
2845 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) in ath9k_hw_set_gpio() argument
2847 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_set_gpio()
2849 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah)) in ath9k_hw_set_gpio()
2854 if (BIT(gpio) & ah->caps.gpio_mask) { in ath9k_hw_set_gpio()
2855 u32 out_addr = AR_DEVID_7010(ah) ? in ath9k_hw_set_gpio()
2858 REG_RMW(ah, out_addr, val << gpio, BIT(gpio)); in ath9k_hw_set_gpio()
2859 } else if (BIT(gpio) & ah->caps.gpio_requested) { in ath9k_hw_set_gpio()
2867 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) in ath9k_hw_setantenna() argument
2869 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
2877 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) in ath9k_hw_getrxfilter() argument
2879 u32 bits = REG_READ(ah, AR_RX_FILTER); in ath9k_hw_getrxfilter()
2880 u32 phybits = REG_READ(ah, AR_PHY_ERR); in ath9k_hw_getrxfilter()
2891 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) in ath9k_hw_setrxfilter() argument
2895 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_setrxfilter()
2897 REG_WRITE(ah, AR_RX_FILTER, bits); in ath9k_hw_setrxfilter()
2904 REG_WRITE(ah, AR_PHY_ERR, phybits); in ath9k_hw_setrxfilter()
2907 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2909 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2911 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_setrxfilter()
2915 bool ath9k_hw_phy_disable(struct ath_hw *ah) in ath9k_hw_phy_disable() argument
2917 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_phy_disable()
2918 ar9003_mci_bt_gain_ctrl(ah); in ath9k_hw_phy_disable()
2920 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) in ath9k_hw_phy_disable()
2923 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_phy_disable()
2924 ah->htc_reset_init = true; in ath9k_hw_phy_disable()
2929 bool ath9k_hw_disable(struct ath_hw *ah) in ath9k_hw_disable() argument
2931 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_disable()
2934 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) in ath9k_hw_disable()
2937 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_disable()
2942 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) in get_antenna_gain() argument
2951 return ah->eep_ops->get_eeprom(ah, gain_param); in get_antenna_gain()
2954 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_apply_txpower() argument
2957 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_apply_txpower()
2972 ah->eep_ops->set_txpower(ah, chan, ctl, in ath9k_hw_apply_txpower()
2973 get_antenna_gain(ah, chan), new_pwr, test); in ath9k_hw_apply_txpower()
2976 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) in ath9k_hw_set_txpowerlimit() argument
2978 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_set_txpowerlimit()
2979 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_txpowerlimit()
2986 ath9k_hw_apply_txpower(ah, chan, test); in ath9k_hw_set_txpowerlimit()
2993 void ath9k_hw_setopmode(struct ath_hw *ah) in ath9k_hw_setopmode() argument
2995 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_setopmode()
2999 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) in ath9k_hw_setmcastfilter() argument
3001 REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ath9k_hw_setmcastfilter()
3002 REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ath9k_hw_setmcastfilter()
3006 void ath9k_hw_write_associd(struct ath_hw *ah) in ath9k_hw_write_associd() argument
3008 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_write_associd()
3010 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); in ath9k_hw_write_associd()
3011 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | in ath9k_hw_write_associd()
3018 u64 ath9k_hw_gettsf64(struct ath_hw *ah) in ath9k_hw_gettsf64() argument
3023 tsf_upper1 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
3025 tsf_lower = REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf64()
3026 tsf_upper2 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
3038 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) in ath9k_hw_settsf64() argument
3040 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ath9k_hw_settsf64()
3041 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ath9k_hw_settsf64()
3045 void ath9k_hw_reset_tsf(struct ath_hw *ah) in ath9k_hw_reset_tsf() argument
3047 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, in ath9k_hw_reset_tsf()
3049 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_reset_tsf()
3052 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); in ath9k_hw_reset_tsf()
3056 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) in ath9k_hw_set_tsfadjust() argument
3059 ah->misc_mode |= AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
3061 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
3065 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_set11nmac2040() argument
3069 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) in ath9k_hw_set11nmac2040()
3074 REG_WRITE(ah, AR_2040_MODE, macmode); in ath9k_hw_set11nmac2040()
3108 u32 ath9k_hw_gettsf32(struct ath_hw *ah) in ath9k_hw_gettsf32() argument
3110 return REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf32()
3114 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) in ath9k_hw_gen_timer_start_tsf2() argument
3116 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start_tsf2()
3119 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); in ath9k_hw_gen_timer_start_tsf2()
3120 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); in ath9k_hw_gen_timer_start_tsf2()
3124 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, in ath_gen_timer_alloc() argument
3130 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_alloc()
3138 !AR_SREV_9300_20_OR_LATER(ah)) in ath_gen_timer_alloc()
3154 ath9k_hw_gen_timer_start_tsf2(ah); in ath_gen_timer_alloc()
3161 void ath9k_hw_gen_timer_start(struct ath_hw *ah, in ath9k_hw_gen_timer_start() argument
3166 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start()
3174 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, in ath9k_hw_gen_timer_start()
3176 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, in ath9k_hw_gen_timer_start()
3178 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_start()
3181 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_start()
3188 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3191 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3202 REG_SET_BIT(ah, AR_IMR_S5, mask); in ath9k_hw_gen_timer_start()
3204 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { in ath9k_hw_gen_timer_start()
3205 ah->imask |= ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_start()
3206 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_start()
3211 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) in ath9k_hw_gen_timer_stop() argument
3213 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_stop()
3216 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_stop()
3219 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_stop()
3224 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_stop()
3230 REG_CLR_BIT(ah, AR_IMR_S5, in ath9k_hw_gen_timer_stop()
3237 ah->imask &= ~ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_stop()
3238 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_stop()
3243 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) in ath_gen_timer_free() argument
3245 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_free()
3256 void ath_gen_timer_isr(struct ath_hw *ah) in ath_gen_timer_isr() argument
3258 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_isr()
3264 trigger_mask = ah->intr_gen_timer_trigger; in ath_gen_timer_isr()
3265 thresh_mask = ah->intr_gen_timer_thresh; in ath_gen_timer_isr()
3365 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) in ath9k_hw_name() argument
3370 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_name()
3373 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3374 ah->hw_version.macRev); in ath9k_hw_name()
3379 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3380 ah->hw_version.macRev, in ath9k_hw_name()
3381 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev in ath9k_hw_name()
3383 ah->hw_version.phyRev); in ath9k_hw_name()