Lines Matching refs:SM
181 (SM(0, AR_PHY_AIC_MON_ENABLE) | in ar9003_aic_cal_start()
182 SM(127, AR_PHY_AIC_CAL_MAX_HOP_COUNT) | in ar9003_aic_cal_start()
183 SM(min_valid_count, AR_PHY_AIC_CAL_MIN_VALID_COUNT) | in ar9003_aic_cal_start()
184 SM(37, AR_PHY_AIC_F_WLAN) | in ar9003_aic_cal_start()
185 SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) | in ar9003_aic_cal_start()
186 SM(0, AR_PHY_AIC_CAL_ENABLE) | in ar9003_aic_cal_start()
187 SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) | in ar9003_aic_cal_start()
188 SM(0, AR_PHY_AIC_ENABLE))); in ar9003_aic_cal_start()
191 (SM(0, AR_PHY_AIC_MON_ENABLE) | in ar9003_aic_cal_start()
192 SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) | in ar9003_aic_cal_start()
193 SM(0, AR_PHY_AIC_CAL_ENABLE) | in ar9003_aic_cal_start()
194 SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) | in ar9003_aic_cal_start()
195 SM(0, AR_PHY_AIC_ENABLE))); in ar9003_aic_cal_start()
198 (SM(8, AR_PHY_AIC_CAL_BT_REF_DELAY) | in ar9003_aic_cal_start()
199 SM(0, AR_PHY_AIC_BT_IDLE_CFG) | in ar9003_aic_cal_start()
200 SM(1, AR_PHY_AIC_STDBY_COND) | in ar9003_aic_cal_start()
201 SM(37, AR_PHY_AIC_STDBY_ROT_ATT_DB) | in ar9003_aic_cal_start()
202 SM(5, AR_PHY_AIC_STDBY_COM_ATT_DB) | in ar9003_aic_cal_start()
203 SM(15, AR_PHY_AIC_RSSI_MAX) | in ar9003_aic_cal_start()
204 SM(0, AR_PHY_AIC_RSSI_MIN))); in ar9003_aic_cal_start()
207 (SM(15, AR_PHY_AIC_RSSI_MAX) | in ar9003_aic_cal_start()
208 SM(0, AR_PHY_AIC_RSSI_MIN))); in ar9003_aic_cal_start()
211 (SM(44, AR_PHY_AIC_RADIO_DELAY) | in ar9003_aic_cal_start()
212 SM(8, AR_PHY_AIC_CAL_STEP_SIZE_CORR) | in ar9003_aic_cal_start()
213 SM(12, AR_PHY_AIC_CAL_ROT_IDX_CORR) | in ar9003_aic_cal_start()
214 SM(2, AR_PHY_AIC_CAL_CONV_CHECK_FACTOR) | in ar9003_aic_cal_start()
215 SM(5, AR_PHY_AIC_ROT_IDX_COUNT_MAX) | in ar9003_aic_cal_start()
216 SM(0, AR_PHY_AIC_CAL_SYNTH_TOGGLE) | in ar9003_aic_cal_start()
217 SM(0, AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX) | in ar9003_aic_cal_start()
218 SM(200, AR_PHY_AIC_CAL_SYNTH_SETTLING))); in ar9003_aic_cal_start()
221 (SM(2, AR_PHY_AIC_MON_MAX_HOP_COUNT) | in ar9003_aic_cal_start()
222 SM(1, AR_PHY_AIC_MON_MIN_STALE_COUNT) | in ar9003_aic_cal_start()
223 SM(1, AR_PHY_AIC_MON_PWR_EST_LONG) | in ar9003_aic_cal_start()
224 SM(2, AR_PHY_AIC_MON_PD_TALLY_SCALING) | in ar9003_aic_cal_start()
225 SM(10, AR_PHY_AIC_MON_PERF_THR) | in ar9003_aic_cal_start()
226 SM(2, AR_PHY_AIC_CAL_TARGET_MAG_SETTING) | in ar9003_aic_cal_start()
227 SM(1, AR_PHY_AIC_CAL_PERF_CHECK_FACTOR) | in ar9003_aic_cal_start()
228 SM(1, AR_PHY_AIC_CAL_PWR_EST_LONG))); in ar9003_aic_cal_start()
231 (SM(2, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) | in ar9003_aic_cal_start()
232 SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) | in ar9003_aic_cal_start()
233 SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) | in ar9003_aic_cal_start()
234 SM(2, AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF) | in ar9003_aic_cal_start()
235 SM(1, AR_PHY_AIC_CAL_COM_ATT_DB_FIXED))); in ar9003_aic_cal_start()
238 (SM(2, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) | in ar9003_aic_cal_start()
239 SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) | in ar9003_aic_cal_start()
240 SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) | in ar9003_aic_cal_start()
241 SM(2, AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF) | in ar9003_aic_cal_start()
242 SM(1, AR_PHY_AIC_CAL_COM_ATT_DB_FIXED))); in ar9003_aic_cal_start()
420 aic->aic_sram[i] = (SM(sram.vga_dir_sign, in ar9003_aic_cal_post_process()
422 SM(sram.vga_quad_sign, in ar9003_aic_cal_post_process()
424 SM(sram.com_att_6db, in ar9003_aic_cal_post_process()
426 SM(sram.valid, in ar9003_aic_cal_post_process()
428 SM(sram.rot_dir_att_db, in ar9003_aic_cal_post_process()
430 SM(sram.rot_quad_att_db, in ar9003_aic_cal_post_process()