Lines Matching refs:REG_SET_BIT
75 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
265 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
458 REG_SET_BIT(ah, 0x9808, 1 << 27); in ar9271_hw_pa_cal()
460 REG_SET_BIT(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC); in ar9271_hw_pa_cal()
462 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1); in ar9271_hw_pa_cal()
464 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I); in ar9271_hw_pa_cal()
466 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF); in ar9271_hw_pa_cal()
529 REG_SET_BIT(ah, AR9285_AN_RF2G6, 1 << 0); in ar9271_hw_pa_cal()
751 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
753 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
754 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
758 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
771 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
772 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
773 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
782 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
860 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
881 REG_SET_BIT(ah, AR_PHY_ADC_CTL, in ar9002_hw_init_cal()