293 			| AR5K_REG_SM(ah->ah_retry_long,  in ath5k_hw_set_tx_retry_limits()
295 			| AR5K_REG_SM(ah->ah_retry_short,  in ath5k_hw_set_tx_retry_limits()
297 			| AR5K_REG_SM(ah->ah_retry_long,  in ath5k_hw_set_tx_retry_limits()
299 			| AR5K_REG_SM(ah->ah_retry_short,  in ath5k_hw_set_tx_retry_limits()
305 			AR5K_REG_SM(ah->ah_retry_long,  in ath5k_hw_set_tx_retry_limits()
307 			| AR5K_REG_SM(ah->ah_retry_long,  in ath5k_hw_set_tx_retry_limits()
309 			| AR5K_REG_SM(max(ah->ah_retry_long, ah->ah_retry_short),  in ath5k_hw_set_tx_retry_limits()
341 		AR5K_REG_SM(tq->tqi_cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |  in ath5k_hw_reset_tx_queue()
342 		AR5K_REG_SM(tq->tqi_cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |  in ath5k_hw_reset_tx_queue()
343 		AR5K_REG_SM(tq->tqi_aifs, AR5K_DCU_LCL_IFS_AIFS),  in ath5k_hw_reset_tx_queue()
367 		ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,  in ath5k_hw_reset_tx_queue()
369 					AR5K_REG_SM(tq->tqi_cbr_overflow_limit,  in ath5k_hw_reset_tx_queue()
383 		ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,  in ath5k_hw_reset_tx_queue()
389 		ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,  in ath5k_hw_reset_tx_queue()
502 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,  in ath5k_hw_reset_tx_queue()
504 					AR5K_REG_SM(ah->ah_txq_imr_txdesc,  in ath5k_hw_reset_tx_queue()
508 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,  in ath5k_hw_reset_tx_queue()
510 					AR5K_REG_SM(ah->ah_txq_imr_txeol,  in ath5k_hw_reset_tx_queue()
517 				AR5K_REG_SM(ah->ah_txq_imr_txurn,  in ath5k_hw_reset_tx_queue()
520 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,  in ath5k_hw_reset_tx_queue()
522 				AR5K_REG_SM(ah->ah_txq_imr_cbrurn,  in ath5k_hw_reset_tx_queue()
526 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,  in ath5k_hw_reset_tx_queue()
530 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,  in ath5k_hw_reset_tx_queue()
638 		eifs_clock = AR5K_REG_SM(eifs_clock, AR5K_IFS1_EIFS);  in ath5k_hw_set_ifs_intervals()
643 		pifs_clock = AR5K_REG_SM(pifs_clock, AR5K_IFS1_PIFS);  in ath5k_hw_set_ifs_intervals()