Lines Matching defs:ath5k_eeprom_info
410 struct ath5k_eeprom_info { struct
413 u16 ee_magic;
414 u16 ee_protect;
415 u16 ee_regdomain;
416 u16 ee_version;
417 u16 ee_header;
418 u16 ee_ant_gain;
419 u8 ee_rfkill_pin;
420 bool ee_rfkill_pol;
421 bool ee_is_hb63;
422 bool ee_serdes;
423 u16 ee_misc0;
424 u16 ee_misc1;
425 u16 ee_misc2;
426 u16 ee_misc3;
427 u16 ee_misc4;
428 u16 ee_misc5;
429 u16 ee_misc6;
430 u16 ee_cck_ofdm_gain_delta;
431 u16 ee_cck_ofdm_power_delta;
432 u16 ee_scaled_cck_delta;
435 u16 ee_i_cal[AR5K_EEPROM_N_MODES];
436 u16 ee_q_cal[AR5K_EEPROM_N_MODES];
437 u16 ee_fixed_bias[AR5K_EEPROM_N_MODES];
438 u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES];
439 u16 ee_xr_power[AR5K_EEPROM_N_MODES];
440 u16 ee_switch_settling[AR5K_EEPROM_N_MODES];
441 u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
442 u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
443 u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
444 u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
445 u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
446 u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
447 u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
448 u16 ee_thr_62[AR5K_EEPROM_N_MODES];
449 u16 ee_xlna_gain[AR5K_EEPROM_N_MODES];
450 u16 ee_xpd[AR5K_EEPROM_N_MODES];
451 u16 ee_x_gain[AR5K_EEPROM_N_MODES];
452 u16 ee_i_gain[AR5K_EEPROM_N_MODES];
453 u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
454 u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
455 u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
456 u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
459 u16 ee_false_detect[AR5K_EEPROM_N_MODES];
462 u8 ee_pd_gains[AR5K_EEPROM_N_MODES];
464 u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
466 u8 ee_n_piers[AR5K_EEPROM_N_MODES];
467 struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
468 struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
469 struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
472 u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
473 struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
474 struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
475 struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
478 u8 ee_ctls;
479 u8 ee_ctl[AR5K_EEPROM_MAX_CTLS];
480 struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
483 s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
484 s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES];
485 s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES];
486 s8 ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
487 s8 ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
488 s8 ee_pd_gain_overlap;
491 u16 ee_spur_chans[AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS];
494 u32 ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];