50 	ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);  in ath5k_hw_start_rx_dma()
63 	ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);  in ath5k_hw_stop_rx_dma()
106 	ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);  in ath5k_hw_set_rxdp()
152 			ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,  in ath5k_hw_start_tx_dma()
157 			ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |  in ath5k_hw_start_tx_dma()
164 		ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);  in ath5k_hw_start_tx_dma()
213 			ath5k_hw_reg_write(ah, 0, AR5K_BSR);  in ath5k_hw_stop_tx_dma()
220 		ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);  in ath5k_hw_stop_tx_dma()
260 			ath5k_hw_reg_write(ah,  in ath5k_hw_stop_tx_dma()
266 			ath5k_hw_reg_write(ah,  in ath5k_hw_stop_tx_dma()
307 		ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);  in ath5k_hw_stop_tx_dma()
431 	ath5k_hw_reg_write(ah, phys_addr, tx_reg);  in ath5k_hw_set_txdp()
477 		ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);  in ath5k_hw_update_tx_triglevel()
638 		ath5k_hw_reg_write(ah, sisr0, AR5K_SISR0);  in ath5k_hw_get_isr()
639 		ath5k_hw_reg_write(ah, sisr1, AR5K_SISR1);  in ath5k_hw_get_isr()
640 		ath5k_hw_reg_write(ah, sisr2, AR5K_SISR2);  in ath5k_hw_get_isr()
641 		ath5k_hw_reg_write(ah, sisr3, AR5K_SISR3);  in ath5k_hw_get_isr()
642 		ath5k_hw_reg_write(ah, sisr4, AR5K_SISR4);  in ath5k_hw_get_isr()
643 		ath5k_hw_reg_write(ah, pisr_clear, AR5K_PISR);  in ath5k_hw_get_isr()
752 		ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);  in ath5k_hw_set_imr()
795 		ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);  in ath5k_hw_set_imr()
796 		ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);  in ath5k_hw_set_imr()
805 		ath5k_hw_reg_write(ah, int_mask, AR5K_IMR);  in ath5k_hw_set_imr()
811 		ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM);  in ath5k_hw_set_imr()
818 		ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);  in ath5k_hw_set_imr()
897 		ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);  in ath5k_hw_dma_stop()