51 	ath5k_hw_reg_read(ah, AR5K_CR);  in ath5k_hw_start_rx_dma()
69 			(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;  in ath5k_hw_stop_rx_dma()
87 	return ath5k_hw_reg_read(ah, AR5K_RXDP);  in ath5k_hw_get_rxdp()
100 	if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {  in ath5k_hw_set_rxdp()
141 		tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);  in ath5k_hw_start_tx_dma()
165 		ath5k_hw_reg_read(ah, AR5K_CR);  in ath5k_hw_start_tx_dma()
200 		tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);  in ath5k_hw_stop_tx_dma()
221 		ath5k_hw_reg_read(ah, AR5K_CR);  in ath5k_hw_stop_tx_dma()
249 			pending = ath5k_hw_reg_read(ah,  in ath5k_hw_stop_tx_dma()
268 				AR5K_REG_SM(ath5k_hw_reg_read(ah,  in ath5k_hw_stop_tx_dma()
285 				pending = ath5k_hw_reg_read(ah,  in ath5k_hw_stop_tx_dma()
379 	return ath5k_hw_reg_read(ah, tx_reg);  in ath5k_hw_get_txdp()
463 	trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),  in ath5k_hw_update_tx_triglevel()
508 	return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;  in ath5k_hw_is_intr_pending()
539 		isr = ath5k_hw_reg_read(ah, AR5K_ISR);  in ath5k_hw_get_isr()
575 		pisr = ath5k_hw_reg_read(ah, AR5K_PISR);  in ath5k_hw_get_isr()
581 		sisr0 = ath5k_hw_reg_read(ah, AR5K_SISR0);  in ath5k_hw_get_isr()
582 		sisr1 = ath5k_hw_reg_read(ah, AR5K_SISR1);  in ath5k_hw_get_isr()
583 		sisr2 = ath5k_hw_reg_read(ah, AR5K_SISR2);  in ath5k_hw_get_isr()
584 		sisr3 = ath5k_hw_reg_read(ah, AR5K_SISR3);  in ath5k_hw_get_isr()
585 		sisr4 = ath5k_hw_reg_read(ah, AR5K_SISR4);  in ath5k_hw_get_isr()
645 		ath5k_hw_reg_read(ah, AR5K_PISR);  in ath5k_hw_get_isr()
753 		ath5k_hw_reg_read(ah, AR5K_IER);  in ath5k_hw_set_imr()
764 		u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)  in ath5k_hw_set_imr()
819 		ath5k_hw_reg_read(ah, AR5K_IER);  in ath5k_hw_set_imr()
901 		ath5k_hw_reg_read(ah, AR5K_ISR);  in ath5k_hw_dma_stop()