Lines Matching refs:mii
78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); in asix_get_phyid()
91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); in asix_get_phyid()
104 return mii_link_ok(&dev->mii); in asix_get_link()
111 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); in asix_ioctl()
176 mii_check_media(&dev->mii, 1, 1); in ax88172_link_reset()
177 mii_ethtool_gset(&dev->mii, &ecmd); in ax88172_link_reset()
208 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits); in asix_phy_reset()
215 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR) in asix_phy_reset()
223 dev->mii.phy_id); in asix_phy_reset()
260 dev->mii.dev = dev->net; in ax88172_bind()
261 dev->mii.mdio_read = asix_mdio_read; in ax88172_bind()
262 dev->mii.mdio_write = asix_mdio_write; in ax88172_bind()
263 dev->mii.phy_id_mask = 0x3f; in ax88172_bind()
264 dev->mii.reg_num_mask = 0x1f; in ax88172_bind()
266 dev->mii.phy_id = asix_read_phy_addr(dev, true); in ax88172_bind()
267 if (dev->mii.phy_id < 0) in ax88172_bind()
268 return dev->mii.phy_id; in ax88172_bind()
276 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, in ax88172_bind()
278 mii_nway_restart(&dev->mii); in ax88172_bind()
419 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772_hw_reset()
509 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
525 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
527 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
529 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
538 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
542 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
546 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
961 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); in marvell_phy_init()
964 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, in marvell_phy_init()
968 reg = asix_mdio_read(dev->net, dev->mii.phy_id, in marvell_phy_init()
974 asix_mdio_write(dev->net, dev->mii.phy_id, in marvell_phy_init()
977 reg = asix_mdio_read(dev->net, dev->mii.phy_id, in marvell_phy_init()
991 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); in rtl8211cl_phy_init()
992 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); in rtl8211cl_phy_init()
993 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, in rtl8211cl_phy_init()
994 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); in rtl8211cl_phy_init()
995 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); in rtl8211cl_phy_init()
998 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); in rtl8211cl_phy_init()
999 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); in rtl8211cl_phy_init()
1000 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); in rtl8211cl_phy_init()
1008 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); in marvell_led_status()
1027 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); in marvell_led_status()
1106 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, in ax88178_reset()
1108 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, in ax88178_reset()
1112 mii_nway_restart(&dev->mii); in ax88178_reset()
1137 mii_check_media(&dev->mii, 1, 1); in ax88178_link_reset()
1138 mii_ethtool_gset(&dev->mii, &ecmd); in ax88178_link_reset()
1252 dev->mii.dev = dev->net; in ax88178_bind()
1253 dev->mii.mdio_read = asix_mdio_read; in ax88178_bind()
1254 dev->mii.mdio_write = asix_mdio_write; in ax88178_bind()
1255 dev->mii.phy_id_mask = 0x1f; in ax88178_bind()
1256 dev->mii.reg_num_mask = 0xff; in ax88178_bind()
1257 dev->mii.supports_gmii = 1; in ax88178_bind()
1259 dev->mii.phy_id = asix_read_phy_addr(dev, true); in ax88178_bind()
1260 if (dev->mii.phy_id < 0) in ax88178_bind()
1261 return dev->mii.phy_id; in ax88178_bind()