Lines Matching refs:BIT
257 #define DAR_IRQSTS1_RX_FRM_PEND BIT(7)
258 #define DAR_IRQSTS1_PLL_UNLOCK_IRQ BIT(6)
259 #define DAR_IRQSTS1_FILTERFAIL_IRQ BIT(5)
260 #define DAR_IRQSTS1_RXWTRMRKIRQ BIT(4)
261 #define DAR_IRQSTS1_CCAIRQ BIT(3)
262 #define DAR_IRQSTS1_RXIRQ BIT(2)
263 #define DAR_IRQSTS1_TXIRQ BIT(1)
264 #define DAR_IRQSTS1_SEQIRQ BIT(0)
267 #define DAR_IRQSTS2_CRCVALID BIT(7)
268 #define DAR_IRQSTS2_CCA BIT(6)
269 #define DAR_IRQSTS2_SRCADDR BIT(5)
270 #define DAR_IRQSTS2_PI BIT(4)
271 #define DAR_IRQSTS2_TMRSTATUS BIT(3)
272 #define DAR_IRQSTS2_ASM_IRQ BIT(2)
273 #define DAR_IRQSTS2_PB_ERR_IRQ BIT(1)
274 #define DAR_IRQSTS2_WAKE_IRQ BIT(0)
277 #define DAR_IRQSTS3_TMR4MSK BIT(7)
278 #define DAR_IRQSTS3_TMR3MSK BIT(6)
279 #define DAR_IRQSTS3_TMR2MSK BIT(5)
280 #define DAR_IRQSTS3_TMR1MSK BIT(4)
281 #define DAR_IRQSTS3_TMR4IRQ BIT(3)
282 #define DAR_IRQSTS3_TMR3IRQ BIT(2)
283 #define DAR_IRQSTS3_TMR2IRQ BIT(1)
284 #define DAR_IRQSTS3_TMR1IRQ BIT(0)
287 #define DAR_PHY_CTRL1_TMRTRIGEN BIT(7)
288 #define DAR_PHY_CTRL1_SLOTTED BIT(6)
289 #define DAR_PHY_CTRL1_CCABFRTX BIT(5)
291 #define DAR_PHY_CTRL1_RXACKRQD BIT(4)
292 #define DAR_PHY_CTRL1_AUTOACK BIT(3)
296 #define DAR_PHY_CTRL2_CRC_MSK BIT(7)
297 #define DAR_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6)
298 #define DAR_PHY_CTRL2_FILTERFAIL_MSK BIT(5)
299 #define DAR_PHY_CTRL2_RX_WMRK_MSK BIT(4)
300 #define DAR_PHY_CTRL2_CCAMSK BIT(3)
301 #define DAR_PHY_CTRL2_RXMSK BIT(2)
302 #define DAR_PHY_CTRL2_TXMSK BIT(1)
303 #define DAR_PHY_CTRL2_SEQMSK BIT(0)
306 #define DAR_PHY_CTRL3_TMR4CMP_EN BIT(7)
307 #define DAR_PHY_CTRL3_TMR3CMP_EN BIT(6)
308 #define DAR_PHY_CTRL3_TMR2CMP_EN BIT(5)
309 #define DAR_PHY_CTRL3_TMR1CMP_EN BIT(4)
310 #define DAR_PHY_CTRL3_ASM_MSK BIT(2)
311 #define DAR_PHY_CTRL3_PB_ERR_MSK BIT(1)
312 #define DAR_PHY_CTRL3_WAKE_MSK BIT(0)
318 #define DAR_PHY_CTRL4_TRCV_MSK BIT(7)
319 #define DAR_PHY_CTRL4_TC3TMOUT BIT(6)
320 #define DAR_PHY_CTRL4_PANCORDNTR0 BIT(5)
324 #define DAR_PHY_CTRL4_TMRLOAD BIT(2)
325 #define DAR_PHY_CTRL4_PROMISCUOUS BIT(1)
326 #define DAR_PHY_CTRL4_TC2PRIME_EN BIT(0)
331 #define DAR_SRC_CTRL_ACK_FRM_PND BIT(3)
332 #define DAR_SRC_CTRL_SRCADDR_EN BIT(2)
333 #define DAR_SRC_CTRL_INDEX_EN BIT(1)
334 #define DAR_SRC_CTRL_INDEX_DISABLE BIT(0)
337 #define DAR_ASM_CTRL1_CLEAR BIT(7)
338 #define DAR_ASM_CTRL1_START BIT(6)
339 #define DAR_ASM_CTRL1_SELFTST BIT(5)
340 #define DAR_ASM_CTRL1_CTR BIT(4)
341 #define DAR_ASM_CTRL1_CBC BIT(3)
342 #define DAR_ASM_CTRL1_AES BIT(2)
343 #define DAR_ASM_CTRL1_LOAD_MAC BIT(1)
348 #define DAR_ASM_CTRL2_TSTPAS BIT(1)
351 #define DAR_CLK_OUT_CTRL_EXTEND BIT(7)
352 #define DAR_CLK_OUT_CTRL_HIZ BIT(6)
353 #define DAR_CLK_OUT_CTRL_SR BIT(5)
354 #define DAR_CLK_OUT_CTRL_DS BIT(4)
355 #define DAR_CLK_OUT_CTRL_EN BIT(3)
359 #define DAR_PWR_MODES_XTAL_READY BIT(5)
360 #define DAR_PWR_MODES_XTALEN BIT(4)
361 #define DAR_PWR_MODES_ASM_CLK_EN BIT(3)
362 #define DAR_PWR_MODES_AUTODOZE BIT(1)
363 #define DAR_PWR_MODES_PMC_MODE BIT(0)
368 #define IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS BIT(5)
369 #define IAR_RX_FRAME_FLT_NS_FT BIT(4)
370 #define IAR_RX_FRAME_FLT_CMD_FT BIT(3)
371 #define IAR_RX_FRAME_FLT_ACK_FT BIT(2)
372 #define IAR_RX_FRAME_FLT_DATA_FT BIT(1)
373 #define IAR_RX_FRAME_FLT_BEACON_FT BIT(0)
378 #define IAR_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3)
379 #define IAR_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2)
380 #define IAR_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1)
381 #define IAR_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0)
384 #define IAR_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7)
385 #define IAR_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6)
389 #define IAR_CCA_CTRL_AGC_FRZ_EN BIT(6)
390 #define IAR_CCA_CTRL_CONT_RSSI_EN BIT(5)
391 #define IAR_CCA_CTRL_LQI_RSSI_NOT_CORR BIT(4)
392 #define IAR_CCA_CTRL_CCA3_AND_NOT_OR BIT(3)
393 #define IAR_CCA_CTRL_POWER_COMP_EN_LQI BIT(2)
394 #define IAR_CCA_CTRL_POWER_COMP_EN_ED BIT(1)
395 #define IAR_CCA_CTRL_POWER_COMP_EN_CCA1 BIT(0)
400 #define IAR_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3)
401 #define IAR_ANT_PAD_CTRL_ANTX_HZ BIT(2)
405 #define IAR_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3)
406 #define IAR_MISC_PAD_CTRL_IRQ_B_OD BIT(2)
407 #define IAR_MISC_PAD_CTRL_NON_GPIO_DS BIT(1)
414 #define IAR_ANT_AGC_CTRL_ANTX_MASK BIT(AR_ANT_AGC_CTRL_ANTX_SHIFT)
420 #define IAR_SOFT_RESET_SOG_RST BIT(7)
421 #define IAR_SOFT_RESET_REGS_RST BIT(4)
422 #define IAR_SOFT_RESET_PLL_RST BIT(3)
423 #define IAR_SOFT_RESET_TX_RST BIT(2)
424 #define IAR_SOFT_RESET_RX_RST BIT(1)
425 #define IAR_SOFT_RESET_SEQ_MGR_RST BIT(0)
430 #define IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5)
431 #define IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4)
432 #define IAR_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3)
433 #define IAR_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2)
434 #define IAR_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1)
435 #define IAR_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0)
438 #define IAR_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7)
439 #define IAR_SEQ_MGR_STS_RX_MODE BIT(6)
440 #define IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5)
441 #define IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4)
442 #define IAR_SEQ_MGR_STS_SEQ_IDLE BIT(3)
446 #define IAR_ABORT_STS_PLL_ABORTED BIT(2)
447 #define IAR_ABORT_STS_TC3_ABORTED BIT(1)
448 #define IAR_ABORT_STS_SW_ABORTED BIT(0)
451 #define IAR_FILTERFAIL_CODE2_PAN_SEL BIT(7)
455 #define IAR_PHY_STS_PLL_UNLOCK BIT(7)
456 #define IAR_PHY_STS_PLL_LOCK_ERR BIT(6)
457 #define IAR_PHY_STS_PLL_LOCK BIT(5)
458 #define IAR_PHY_STS_CRCVALID BIT(3)
459 #define IAR_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2)
460 #define IAR_PHY_STS_SFD_DET BIT(1)
461 #define IAR_PHY_STS_PREAMBLE_DET BIT(0)
464 #define IAR_TEST_MODE_CTRL_HOT_ANT BIT(4)
465 #define IAR_TEST_MODE_CTRL_IDEAL_RSSI_EN BIT(3)
466 #define IAR_TEST_MODE_CTRL_IDEAL_PFC_EN BIT(2)
467 #define IAR_TEST_MODE_CTRL_CONTINUOUS_EN BIT(1)
468 #define IAR_TEST_MODE_CTRL_FPGA_EN BIT(0)
471 #define IAR_DTM_CTRL1_ATM_LOCKED BIT(7)
472 #define IAR_DTM_CTRL1_DTM_EN BIT(6)
473 #define IAR_DTM_CTRL1_PAGE5 BIT(5)
474 #define IAR_DTM_CTRL1_PAGE4 BIT(4)
475 #define IAR_DTM_CTRL1_PAGE3 BIT(3)
476 #define IAR_DTM_CTRL1_PAGE2 BIT(2)
477 #define IAR_DTM_CTRL1_PAGE1 BIT(1)
478 #define IAR_DTM_CTRL1_PAGE0 BIT(0)
481 #define IAR_TX_MODE_CTRL_TX_INV BIT(4)
482 #define IAR_TX_MODE_CTRL_BT_EN BIT(3)
483 #define IAR_TX_MODE_CTRL_DTS2 BIT(2)
484 #define IAR_TX_MODE_CTRL_DTS1 BIT(1)
485 #define IAR_TX_MODE_CTRL_DTS0 BIT(0)