447 	struct mcr20a_local *lp = context;  in mcr20a_write_tx_buf_complete()  local
450 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_write_tx_buf_complete()
452 	lp->reg_msg.complete = NULL;  in mcr20a_write_tx_buf_complete()
453 	lp->reg_cmd[0]	= MCR20A_WRITE_REG(DAR_PHY_CTRL1);  in mcr20a_write_tx_buf_complete()
454 	lp->reg_data[0] = MCR20A_XCVSEQ_TX;  in mcr20a_write_tx_buf_complete()
455 	lp->reg_xfer_data.len = 1;  in mcr20a_write_tx_buf_complete()
457 	ret = spi_async(lp->spi, &lp->reg_msg);  in mcr20a_write_tx_buf_complete()
459 		dev_err(printdev(lp), "failed to set SEQ TX\n");  in mcr20a_write_tx_buf_complete()
465 	struct mcr20a_local *lp = hw->priv;  in mcr20a_xmit()  local
467 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_xmit()
469 	lp->tx_skb = skb;  in mcr20a_xmit()
474 	lp->is_tx = 1;  in mcr20a_xmit()
476 	lp->reg_msg.complete	= NULL;  in mcr20a_xmit()
477 	lp->reg_cmd[0]		= MCR20A_WRITE_REG(DAR_PHY_CTRL1);  in mcr20a_xmit()
478 	lp->reg_data[0]		= MCR20A_XCVSEQ_IDLE;  in mcr20a_xmit()
479 	lp->reg_xfer_data.len	= 1;  in mcr20a_xmit()
481 	return spi_async(lp->spi, &lp->reg_msg);  in mcr20a_xmit()
495 	struct mcr20a_local *lp = hw->priv;  in mcr20a_set_channel()  local
498 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_set_channel()
501 	ret = regmap_write(lp->regmap_dar, DAR_PLL_INT0, PLL_INT[channel - 11]);  in mcr20a_set_channel()
504 	ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_LSB, 0x00);  in mcr20a_set_channel()
507 	ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_MSB,  in mcr20a_set_channel()
518 	struct mcr20a_local *lp = hw->priv;  in mcr20a_start()  local
521 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_start()
524 	dev_dbg(printdev(lp), "no slotted operation\n");  in mcr20a_start()
525 	ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,  in mcr20a_start()
531 	enable_irq(lp->spi->irq);  in mcr20a_start()
534 	ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL2,  in mcr20a_start()
540 	dev_dbg(printdev(lp), "start the RX sequence\n");  in mcr20a_start()
541 	ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,  in mcr20a_start()
552 	struct mcr20a_local *lp = hw->priv;  in mcr20a_stop()  local
554 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_stop()
557 	regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,  in mcr20a_stop()
561 	disable_irq(lp->spi->irq);  in mcr20a_stop()
569 	struct mcr20a_local *lp = hw->priv;  in mcr20a_set_hw_addr_filt()  local
571 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_set_hw_addr_filt()
576 		regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_LSB, addr);  in mcr20a_set_hw_addr_filt()
577 		regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_MSB, addr >> 8);  in mcr20a_set_hw_addr_filt()
583 		regmap_write(lp->regmap_iar, IAR_MACPANID0_LSB, pan);  in mcr20a_set_hw_addr_filt()
584 		regmap_write(lp->regmap_iar, IAR_MACPANID0_MSB, pan >> 8);  in mcr20a_set_hw_addr_filt()
592 			regmap_write(lp->regmap_iar,  in mcr20a_set_hw_addr_filt()
598 			regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,  in mcr20a_set_hw_addr_filt()
601 			regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,  in mcr20a_set_hw_addr_filt()
619 	struct mcr20a_local *lp = hw->priv;  in mcr20a_set_txpower()  local
622 	dev_dbg(printdev(lp), "%s(%d)\n", __func__, mbm);  in mcr20a_set_txpower()
624 	for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {  in mcr20a_set_txpower()
625 		if (lp->hw->phy->supported.tx_powers[i] == mbm)  in mcr20a_set_txpower()
626 			return regmap_write(lp->regmap_dar, DAR_PA_PWR,  in mcr20a_set_txpower()
640 	struct mcr20a_local *lp = hw->priv;  in mcr20a_set_cca_mode()  local
645 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_set_cca_mode()
672 	ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,  in mcr20a_set_cca_mode()
680 			ret = regmap_update_bits(lp->regmap_iar, IAR_CCA_CTRL,  in mcr20a_set_cca_mode()
684 			ret = regmap_update_bits(lp->regmap_iar,  in mcr20a_set_cca_mode()
699 	struct mcr20a_local *lp = hw->priv;  in mcr20a_set_cca_ed_level()  local
702 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_set_cca_ed_level()
706 			return regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, i);  in mcr20a_set_cca_ed_level()
715 	struct mcr20a_local *lp = hw->priv;  in mcr20a_set_promiscuous_mode()  local
719 	dev_dbg(printdev(lp), "%s(%d)\n", __func__, on);  in mcr20a_set_promiscuous_mode()
727 		ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,  in mcr20a_set_promiscuous_mode()
733 		ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,  in mcr20a_set_promiscuous_mode()
738 		ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,  in mcr20a_set_promiscuous_mode()
743 		ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,  in mcr20a_set_promiscuous_mode()
770 mcr20a_request_rx(struct mcr20a_local *lp)  in mcr20a_request_rx()  argument
772 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_request_rx()
775 	regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,  in mcr20a_request_rx()
784 	struct mcr20a_local *lp = context;  in mcr20a_handle_rx_read_buf_complete()  local
785 	u8 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK;  in mcr20a_handle_rx_read_buf_complete()
788 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_handle_rx_read_buf_complete()
790 	dev_dbg(printdev(lp), "RX is done\n");  in mcr20a_handle_rx_read_buf_complete()
793 		dev_vdbg(&lp->spi->dev, "corrupted frame received\n");  in mcr20a_handle_rx_read_buf_complete()
803 	__skb_put_data(skb, lp->rx_buf, len);  in mcr20a_handle_rx_read_buf_complete()
804 	ieee802154_rx_irqsafe(lp->hw, skb, lp->rx_lqi[0]);  in mcr20a_handle_rx_read_buf_complete()
807 			     lp->rx_buf, len, 0);  in mcr20a_handle_rx_read_buf_complete()
808 	pr_debug("mcr20a rx: lqi: %02hhx\n", lp->rx_lqi[0]);  in mcr20a_handle_rx_read_buf_complete()
811 	mcr20a_request_rx(lp);  in mcr20a_handle_rx_read_buf_complete()
817 	struct mcr20a_local *lp = context;  in mcr20a_handle_rx_read_len_complete()  local
821 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_handle_rx_read_len_complete()
824 	len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK;  in mcr20a_handle_rx_read_len_complete()
825 	dev_dbg(printdev(lp), "frame len : %d\n", len);  in mcr20a_handle_rx_read_len_complete()
828 	lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete;  in mcr20a_handle_rx_read_len_complete()
829 	lp->rx_header[0] = MCR20A_BURST_READ_PACKET_BUF;  in mcr20a_handle_rx_read_len_complete()
830 	lp->rx_xfer_buf.len = len;  in mcr20a_handle_rx_read_len_complete()
832 	ret = spi_async(lp->spi, &lp->rx_buf_msg);  in mcr20a_handle_rx_read_len_complete()
834 		dev_err(printdev(lp), "failed to read rx buffer length\n");  in mcr20a_handle_rx_read_len_complete()
838 mcr20a_handle_rx(struct mcr20a_local *lp)  in mcr20a_handle_rx()  argument
840 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_handle_rx()
841 	lp->reg_msg.complete = mcr20a_handle_rx_read_len_complete;  in mcr20a_handle_rx()
842 	lp->reg_cmd[0] = MCR20A_READ_REG(DAR_RX_FRM_LEN);  in mcr20a_handle_rx()
843 	lp->reg_xfer_data.len	= 1;  in mcr20a_handle_rx()
845 	return spi_async(lp->spi, &lp->reg_msg);  in mcr20a_handle_rx()
849 mcr20a_handle_tx_complete(struct mcr20a_local *lp)  in mcr20a_handle_tx_complete()  argument
851 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_handle_tx_complete()
853 	ieee802154_xmit_complete(lp->hw, lp->tx_skb, false);  in mcr20a_handle_tx_complete()
855 	return mcr20a_request_rx(lp);  in mcr20a_handle_tx_complete()
859 mcr20a_handle_tx(struct mcr20a_local *lp)  in mcr20a_handle_tx()  argument
863 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_handle_tx()
866 	lp->tx_header[0]	= MCR20A_BURST_WRITE_PACKET_BUF;  in mcr20a_handle_tx()
868 	lp->tx_len[0]		= lp->tx_skb->len + 2;  in mcr20a_handle_tx()
869 	lp->tx_xfer_buf.tx_buf	= lp->tx_skb->data;  in mcr20a_handle_tx()
871 	lp->tx_xfer_buf.len	= lp->tx_skb->len + 1;  in mcr20a_handle_tx()
873 	ret = spi_async(lp->spi, &lp->tx_buf_msg);  in mcr20a_handle_tx()
875 		dev_err(printdev(lp), "SPI write Failed for TX buf\n");  in mcr20a_handle_tx()
885 	struct mcr20a_local *lp = context;  in mcr20a_irq_clean_complete()  local
886 	u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK;  in mcr20a_irq_clean_complete()
888 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_irq_clean_complete()
890 	enable_irq(lp->spi->irq);  in mcr20a_irq_clean_complete()
892 	dev_dbg(printdev(lp), "IRQ STA1 (%02x) STA2 (%02x)\n",  in mcr20a_irq_clean_complete()
893 		lp->irq_data[DAR_IRQ_STS1], lp->irq_data[DAR_IRQ_STS2]);  in mcr20a_irq_clean_complete()
898 		if (lp->is_tx) {  in mcr20a_irq_clean_complete()
899 			lp->is_tx = 0;  in mcr20a_irq_clean_complete()
900 			dev_dbg(printdev(lp), "TX is done. No ACK\n");  in mcr20a_irq_clean_complete()
901 			mcr20a_handle_tx_complete(lp);  in mcr20a_irq_clean_complete()
906 		dev_dbg(printdev(lp), "RX is starting\n");  in mcr20a_irq_clean_complete()
907 		mcr20a_handle_rx(lp);  in mcr20a_irq_clean_complete()
910 		if (lp->is_tx) {  in mcr20a_irq_clean_complete()
912 			lp->is_tx = 0;  in mcr20a_irq_clean_complete()
913 			dev_dbg(printdev(lp), "TX is done. Get ACK\n");  in mcr20a_irq_clean_complete()
914 			mcr20a_handle_tx_complete(lp);  in mcr20a_irq_clean_complete()
917 			dev_dbg(printdev(lp), "RX is starting\n");  in mcr20a_irq_clean_complete()
918 			mcr20a_handle_rx(lp);  in mcr20a_irq_clean_complete()
922 		if (lp->is_tx) {  in mcr20a_irq_clean_complete()
923 			dev_dbg(printdev(lp), "TX is starting\n");  in mcr20a_irq_clean_complete()
924 			mcr20a_handle_tx(lp);  in mcr20a_irq_clean_complete()
926 			dev_dbg(printdev(lp), "MCR20A is stop\n");  in mcr20a_irq_clean_complete()
935 	struct mcr20a_local *lp = context;  in mcr20a_irq_status_complete()  local
937 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_irq_status_complete()
938 	regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,  in mcr20a_irq_status_complete()
941 	lp->reg_msg.complete = mcr20a_irq_clean_complete;  in mcr20a_irq_status_complete()
942 	lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_IRQ_STS1);  in mcr20a_irq_status_complete()
943 	memcpy(lp->reg_data, lp->irq_data, MCR20A_IRQSTS_NUM);  in mcr20a_irq_status_complete()
944 	lp->reg_xfer_data.len = MCR20A_IRQSTS_NUM;  in mcr20a_irq_status_complete()
946 	ret = spi_async(lp->spi, &lp->reg_msg);  in mcr20a_irq_status_complete()
949 		dev_err(printdev(lp), "failed to clean irq status\n");  in mcr20a_irq_status_complete()
954 	struct mcr20a_local *lp = data;  in mcr20a_irq_isr()  local
959 	lp->irq_header[0] = MCR20A_READ_REG(DAR_IRQ_STS1);  in mcr20a_irq_isr()
961 	ret = spi_async(lp->spi, &lp->irq_msg);  in mcr20a_irq_isr()
970 static void mcr20a_hw_setup(struct mcr20a_local *lp)  in mcr20a_hw_setup()  argument
973 	struct ieee802154_hw *hw = lp->hw;  in mcr20a_hw_setup()
974 	struct wpan_phy *phy = lp->hw->phy;  in mcr20a_hw_setup()
976 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_hw_setup()
1012 mcr20a_setup_tx_spi_messages(struct mcr20a_local *lp)  in mcr20a_setup_tx_spi_messages()  argument
1014 	spi_message_init(&lp->tx_buf_msg);  in mcr20a_setup_tx_spi_messages()
1015 	lp->tx_buf_msg.context = lp;  in mcr20a_setup_tx_spi_messages()
1016 	lp->tx_buf_msg.complete = mcr20a_write_tx_buf_complete;  in mcr20a_setup_tx_spi_messages()
1018 	lp->tx_xfer_header.len = 1;  in mcr20a_setup_tx_spi_messages()
1019 	lp->tx_xfer_header.tx_buf = lp->tx_header;  in mcr20a_setup_tx_spi_messages()
1021 	lp->tx_xfer_len.len = 1;  in mcr20a_setup_tx_spi_messages()
1022 	lp->tx_xfer_len.tx_buf = lp->tx_len;  in mcr20a_setup_tx_spi_messages()
1024 	spi_message_add_tail(&lp->tx_xfer_header, &lp->tx_buf_msg);  in mcr20a_setup_tx_spi_messages()
1025 	spi_message_add_tail(&lp->tx_xfer_len, &lp->tx_buf_msg);  in mcr20a_setup_tx_spi_messages()
1026 	spi_message_add_tail(&lp->tx_xfer_buf, &lp->tx_buf_msg);  in mcr20a_setup_tx_spi_messages()
1030 mcr20a_setup_rx_spi_messages(struct mcr20a_local *lp)  in mcr20a_setup_rx_spi_messages()  argument
1032 	spi_message_init(&lp->reg_msg);  in mcr20a_setup_rx_spi_messages()
1033 	lp->reg_msg.context = lp;  in mcr20a_setup_rx_spi_messages()
1035 	lp->reg_xfer_cmd.len = 1;  in mcr20a_setup_rx_spi_messages()
1036 	lp->reg_xfer_cmd.tx_buf = lp->reg_cmd;  in mcr20a_setup_rx_spi_messages()
1037 	lp->reg_xfer_cmd.rx_buf = lp->reg_cmd;  in mcr20a_setup_rx_spi_messages()
1039 	lp->reg_xfer_data.rx_buf = lp->reg_data;  in mcr20a_setup_rx_spi_messages()
1040 	lp->reg_xfer_data.tx_buf = lp->reg_data;  in mcr20a_setup_rx_spi_messages()
1042 	spi_message_add_tail(&lp->reg_xfer_cmd, &lp->reg_msg);  in mcr20a_setup_rx_spi_messages()
1043 	spi_message_add_tail(&lp->reg_xfer_data, &lp->reg_msg);  in mcr20a_setup_rx_spi_messages()
1045 	spi_message_init(&lp->rx_buf_msg);  in mcr20a_setup_rx_spi_messages()
1046 	lp->rx_buf_msg.context = lp;  in mcr20a_setup_rx_spi_messages()
1047 	lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete;  in mcr20a_setup_rx_spi_messages()
1048 	lp->rx_xfer_header.len = 1;  in mcr20a_setup_rx_spi_messages()
1049 	lp->rx_xfer_header.tx_buf = lp->rx_header;  in mcr20a_setup_rx_spi_messages()
1050 	lp->rx_xfer_header.rx_buf = lp->rx_header;  in mcr20a_setup_rx_spi_messages()
1052 	lp->rx_xfer_buf.rx_buf = lp->rx_buf;  in mcr20a_setup_rx_spi_messages()
1054 	lp->rx_xfer_lqi.len = 1;  in mcr20a_setup_rx_spi_messages()
1055 	lp->rx_xfer_lqi.rx_buf = lp->rx_lqi;  in mcr20a_setup_rx_spi_messages()
1057 	spi_message_add_tail(&lp->rx_xfer_header, &lp->rx_buf_msg);  in mcr20a_setup_rx_spi_messages()
1058 	spi_message_add_tail(&lp->rx_xfer_buf, &lp->rx_buf_msg);  in mcr20a_setup_rx_spi_messages()
1059 	spi_message_add_tail(&lp->rx_xfer_lqi, &lp->rx_buf_msg);  in mcr20a_setup_rx_spi_messages()
1063 mcr20a_setup_irq_spi_messages(struct mcr20a_local *lp)  in mcr20a_setup_irq_spi_messages()  argument
1065 	spi_message_init(&lp->irq_msg);  in mcr20a_setup_irq_spi_messages()
1066 	lp->irq_msg.context		= lp;  in mcr20a_setup_irq_spi_messages()
1067 	lp->irq_msg.complete	= mcr20a_irq_status_complete;  in mcr20a_setup_irq_spi_messages()
1068 	lp->irq_xfer_header.len	= 1;  in mcr20a_setup_irq_spi_messages()
1069 	lp->irq_xfer_header.tx_buf = lp->irq_header;  in mcr20a_setup_irq_spi_messages()
1070 	lp->irq_xfer_header.rx_buf = lp->irq_header;  in mcr20a_setup_irq_spi_messages()
1072 	lp->irq_xfer_data.len	= MCR20A_IRQSTS_NUM;  in mcr20a_setup_irq_spi_messages()
1073 	lp->irq_xfer_data.rx_buf = lp->irq_data;  in mcr20a_setup_irq_spi_messages()
1075 	spi_message_add_tail(&lp->irq_xfer_header, &lp->irq_msg);  in mcr20a_setup_irq_spi_messages()
1076 	spi_message_add_tail(&lp->irq_xfer_data, &lp->irq_msg);  in mcr20a_setup_irq_spi_messages()
1080 mcr20a_phy_init(struct mcr20a_local *lp)  in mcr20a_phy_init()  argument
1086 	dev_dbg(printdev(lp), "%s\n", __func__);  in mcr20a_phy_init()
1089 	ret = regmap_write(lp->regmap_iar, IAR_MISC_PAD_CTRL, 0x02);  in mcr20a_phy_init()
1096 	ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS1, 0xEF);  in mcr20a_phy_init()
1101 	ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS2,  in mcr20a_phy_init()
1108 	ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS3, 0xFF);  in mcr20a_phy_init()
1113 	ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,  in mcr20a_phy_init()
1117 	ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL2, 0xFF);  in mcr20a_phy_init()
1122 	ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL3,  in mcr20a_phy_init()
1131 	ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL,  in mcr20a_phy_init()
1139 	ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,  in mcr20a_phy_init()
1147 	dev_info(printdev(lp), "MCR20A DAR overwrites version: 0x%02x\n",  in mcr20a_phy_init()
1151 	ret = regmap_write(lp->regmap_dar, DAR_OVERWRITE_VER,  in mcr20a_phy_init()
1157 	ret = regmap_multi_reg_write(lp->regmap_iar, mar20a_iar_overwrites,  in mcr20a_phy_init()
1163 	dev_dbg(printdev(lp), "clear HW indirect queue\n");  in mcr20a_phy_init()
1169 		ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, phy_reg);  in mcr20a_phy_init()
1176 	ret = regmap_read(lp->regmap_iar, IAR_DUAL_PAN_CTRL, &phy_reg);  in mcr20a_phy_init()
1186 	ret = regmap_write(lp->regmap_iar, IAR_DUAL_PAN_CTRL, phy_reg);  in mcr20a_phy_init()
1191 	ret = regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, 0x4B);  in mcr20a_phy_init()
1196 	ret = regmap_write(lp->regmap_iar, IAR_TMR_PRESCALE, 0x05);  in mcr20a_phy_init()
1201 	ret = regmap_update_bits(lp->regmap_dar, DAR_PWR_MODES,  in mcr20a_phy_init()
1208 	ret = regmap_update_bits(lp->regmap_dar, DAR_CLK_OUT_CTRL,  in mcr20a_phy_init()
1223 	struct mcr20a_local *lp;  in mcr20a_probe()  local
1251 	hw = ieee802154_alloc_hw(sizeof(*lp), &mcr20a_hw_ops);  in mcr20a_probe()
1258 	lp = hw->priv;  in mcr20a_probe()
1259 	lp->hw = hw;  in mcr20a_probe()
1260 	lp->spi = spi;  in mcr20a_probe()
1267 	lp->buf = devm_kzalloc(&spi->dev, SPI_COMMAND_BUFFER, GFP_KERNEL);  in mcr20a_probe()
1269 	if (!lp->buf) {  in mcr20a_probe()
1274 	mcr20a_setup_tx_spi_messages(lp);  in mcr20a_probe()
1275 	mcr20a_setup_rx_spi_messages(lp);  in mcr20a_probe()
1276 	mcr20a_setup_irq_spi_messages(lp);  in mcr20a_probe()
1279 	lp->regmap_dar = devm_regmap_init_spi(spi, &mcr20a_dar_regmap);  in mcr20a_probe()
1280 	if (IS_ERR(lp->regmap_dar)) {  in mcr20a_probe()
1281 		ret = PTR_ERR(lp->regmap_dar);  in mcr20a_probe()
1287 	lp->regmap_iar = devm_regmap_init_spi(spi, &mcr20a_iar_regmap);  in mcr20a_probe()
1288 	if (IS_ERR(lp->regmap_iar)) {  in mcr20a_probe()
1289 		ret = PTR_ERR(lp->regmap_iar);  in mcr20a_probe()
1294 	mcr20a_hw_setup(lp);  in mcr20a_probe()
1296 	spi_set_drvdata(spi, lp);  in mcr20a_probe()
1298 	ret = mcr20a_phy_init(lp);  in mcr20a_probe()
1309 			       irq_type, dev_name(&spi->dev), lp);  in mcr20a_probe()
1328 	ieee802154_free_hw(lp->hw);  in mcr20a_probe()
1335 	struct mcr20a_local *lp = spi_get_drvdata(spi);  in mcr20a_remove()  local
1339 	ieee802154_unregister_hw(lp->hw);  in mcr20a_remove()
1340 	ieee802154_free_hw(lp->hw);  in mcr20a_remove()