100 	int iobase;  member
149 #define RBR(iobase)	(iobase+0)  argument
150 #define THR(iobase)	(iobase+0)  argument
151 #define IER(iobase)	(iobase+1)  argument
152 #define IIR(iobase)	(iobase+2)  argument
153 #define FCR(iobase)	(iobase+2)  argument
154 #define LCR(iobase)	(iobase+3)  argument
155 #define MCR(iobase)	(iobase+4)  argument
156 #define LSR(iobase)	(iobase+5)  argument
157 #define MSR(iobase)	(iobase+6)  argument
158 #define SCR(iobase)	(iobase+7)  argument
159 #define DLL(iobase)	(iobase+0)  argument
160 #define DLM(iobase)	(iobase+1)  argument
291 static void fpga_reset(int iobase)  in fpga_reset()  argument
293 	outb(0, IER(iobase));  in fpga_reset()
294 	outb(LCR_DLAB | LCR_BIT5, LCR(iobase));  in fpga_reset()
295 	outb(1, DLL(iobase));  in fpga_reset()
296 	outb(0, DLM(iobase));  in fpga_reset()
298 	outb(LCR_BIT5, LCR(iobase));  in fpga_reset()
299 	inb(LSR(iobase));  in fpga_reset()
300 	inb(MSR(iobase));  in fpga_reset()
302 	outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));  in fpga_reset()
305 	outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));  in fpga_reset()
313 static int fpga_write(int iobase, unsigned char wrd)  in fpga_write()  argument
321 		outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));  in fpga_write()
323 		outb(0xfc, THR(iobase));  in fpga_write()
324 		while ((inb(LSR(iobase)) & LSR_TSRE) == 0)  in fpga_write()
429 static int fpga_download(int iobase, int bitrate)  in fpga_download()  argument
438 	fpga_reset(iobase);  in fpga_download()
440 		if (fpga_write(iobase, pbits[i])) {  in fpga_download()
446 	fpga_write(iobase, 0xFF);  in fpga_download()
447 	rc = inb(MSR(iobase));		/* check DONE signal */  in fpga_download()
494 static enum uart yam_check_uart(unsigned int iobase)  in yam_check_uart()  argument
501 	b1 = inb(MCR(iobase));  in yam_check_uart()
502 	outb(b1 | 0x10, MCR(iobase));	/* loopback mode */  in yam_check_uart()
503 	b2 = inb(MSR(iobase));  in yam_check_uart()
504 	outb(0x1a, MCR(iobase));  in yam_check_uart()
505 	b3 = inb(MSR(iobase)) & 0xf0;  in yam_check_uart()
506 	outb(b1, MCR(iobase));		/* restore old values */  in yam_check_uart()
507 	outb(b2, MSR(iobase));  in yam_check_uart()
510 	inb(RBR(iobase));  in yam_check_uart()
511 	inb(RBR(iobase));  in yam_check_uart()
512 	outb(0x01, FCR(iobase));	/* enable FIFOs */  in yam_check_uart()
513 	u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];  in yam_check_uart()
515 		outb(0x5a, SCR(iobase));  in yam_check_uart()
516 		b1 = inb(SCR(iobase));  in yam_check_uart()
517 		outb(0xa5, SCR(iobase));  in yam_check_uart()
518 		b2 = inb(SCR(iobase));  in yam_check_uart()
804 	seq_printf(seq, "  IoBase   0x%x\n", yp->iobase);  in yam_seq_show()
980 			yp->iobase = yi.cfg.iobase;  in yam_siocdevprivate()
981 			dev->base_addr = yi.cfg.iobase;  in yam_siocdevprivate()
1035 		yi.cfg.iobase = yp->iobase;  in yam_siocdevprivate()
1085 	yp->iobase = 0;  in yam_setup()
1095 	dev->base_addr = yp->iobase;  in yam_setup()