92 #define RBR(iobase) (iobase+0)  argument
93 #define THR(iobase) (iobase+0)  argument
94 #define IER(iobase) (iobase+1)  argument
95 #define IIR(iobase) (iobase+2)  argument
96 #define FCR(iobase) (iobase+2)  argument
97 #define LCR(iobase) (iobase+3)  argument
98 #define MCR(iobase) (iobase+4)  argument
99 #define LSR(iobase) (iobase+5)  argument
100 #define MSR(iobase) (iobase+6)  argument
101 #define SCR(iobase) (iobase+7)  argument
102 #define DLL(iobase) (iobase+0)  argument
103 #define DLM(iobase) (iobase+1)  argument
341 static enum uart ser12_check_uart(unsigned int iobase)  in ser12_check_uart()  argument
348 	b1 = inb(MCR(iobase));  in ser12_check_uart()
349 	outb(b1 | 0x10, MCR(iobase));	/* loopback mode */  in ser12_check_uart()
350 	b2 = inb(MSR(iobase));  in ser12_check_uart()
351 	outb(0x1a, MCR(iobase));  in ser12_check_uart()
352 	b3 = inb(MSR(iobase)) & 0xf0;  in ser12_check_uart()
353 	outb(b1, MCR(iobase));			/* restore old values */  in ser12_check_uart()
354 	outb(b2, MSR(iobase));  in ser12_check_uart()
357 	inb(RBR(iobase));  in ser12_check_uart()
358 	inb(RBR(iobase));  in ser12_check_uart()
359 	outb(0x01, FCR(iobase));		/* enable FIFOs */  in ser12_check_uart()
360 	u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];  in ser12_check_uart()
362 		outb(0x5a, SCR(iobase));  in ser12_check_uart()
363 		b1 = inb(SCR(iobase));  in ser12_check_uart()
364 		outb(0xa5, SCR(iobase));  in ser12_check_uart()
365 		b2 = inb(SCR(iobase));  in ser12_check_uart()
570 static int iobase[NR_PORTS] = { 0x3f8, };  variable
576 module_param_hw_array(iobase, int, ioport, NULL, 0);
577 MODULE_PARM_DESC(iobase, "baycom io base address");
608 			iobase[i] = irq[i] = 0;  in init_baycomserfdx()
612 				       ifname, iobase[i], irq[i], 0);  in init_baycomserfdx()
666         iobase[nr_dev] = ints[1];  in baycom_ser_fdx_setup()