132 	do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
134 	do { WRITE_REG(priv, regIMR, 0); } while (0)
174 	WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));  in bdx_fifo_init()
175 	WRITE_REG(priv, reg_CFG1, H32_64(f->da));  in bdx_fifo_init()
346 		WRITE_REG(priv, regINIT_SEMAPHORE, 1);  in bdx_fw_load()
374 	WRITE_REG(priv, regUNC_MAC2_A, val);  in bdx_restore_mac()
376 	WRITE_REG(priv, regUNC_MAC1_A, val);  in bdx_restore_mac()
378 	WRITE_REG(priv, regUNC_MAC0_A, val);  in bdx_restore_mac()
399 	WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);  in bdx_hw_start()
400 	WRITE_REG(priv, regPAUSE_QUANT, 0x96);  in bdx_hw_start()
401 	WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);  in bdx_hw_start()
402 	WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);  in bdx_hw_start()
403 	WRITE_REG(priv, regRX_FULLNESS, 0);  in bdx_hw_start()
404 	WRITE_REG(priv, regTX_FULLNESS, 0);  in bdx_hw_start()
405 	WRITE_REG(priv, regCTRLST,  in bdx_hw_start()
408 	WRITE_REG(priv, regVGLB, 0);  in bdx_hw_start()
409 	WRITE_REG(priv, regMAX_FRAME_A,  in bdx_hw_start()
413 	WRITE_REG(priv, regRDINTCM0, priv->rdintcm);  in bdx_hw_start()
414 	WRITE_REG(priv, regRDINTCM2, 0);	/*cpu_to_le32(rcm.val)); */  in bdx_hw_start()
417 	WRITE_REG(priv, regTDINTCM0, priv->tdintcm);	/* old val = 0x300064 */  in bdx_hw_start()
423 	WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |  in bdx_hw_start()
483 		WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);  in bdx_hw_reset()
486 		WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);  in bdx_hw_reset()
506 	WRITE_REG(priv, regGMAC_RXF_A, 0);  in bdx_sw_reset()
509 	WRITE_REG(priv, regDIS_PORT, 1);  in bdx_sw_reset()
511 	WRITE_REG(priv, regDIS_QU, 1);  in bdx_sw_reset()
522 	WRITE_REG(priv, regRDINTCM0, 0);  in bdx_sw_reset()
523 	WRITE_REG(priv, regTDINTCM0, 0);  in bdx_sw_reset()
524 	WRITE_REG(priv, regIMR, 0);  in bdx_sw_reset()
528 	WRITE_REG(priv, regRST_QU, 1);  in bdx_sw_reset()
530 	WRITE_REG(priv, regRST_PORT, 1);  in bdx_sw_reset()
535 		WRITE_REG(priv, i, 0);  in bdx_sw_reset()
537 	WRITE_REG(priv, regDIS_PORT, 0);  in bdx_sw_reset()
539 	WRITE_REG(priv, regDIS_QU, 0);  in bdx_sw_reset()
541 	WRITE_REG(priv, regRST_QU, 0);  in bdx_sw_reset()
543 	WRITE_REG(priv, regRST_PORT, 0);  in bdx_sw_reset()
682 		WRITE_REG(priv, data[1], data[2]);  in bdx_siocdevprivate()
720 	WRITE_REG(priv, reg, val);  in __bdx_vlan_rx_vid()
785 			WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);  in bdx_setmulti()
793 			WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);  in bdx_setmulti()
796 			WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);  in bdx_setmulti()
797 			WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);  in bdx_setmulti()
812 			WRITE_REG(priv, reg, val);  in bdx_setmulti()
819 	WRITE_REG(priv, regGMAC_RXF_A, rxf_val);  in bdx_setmulti()
1121 	WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);  in bdx_rx_alloc_skbs()
1291 	WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);  in bdx_rx_receive()
1657 		WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);  in bdx_tx_transmit()
1661 			WRITE_REG(priv, f->m.reg_WPTR,  in bdx_tx_transmit()
1670 	WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);  in bdx_tx_transmit()
1728 	WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);  in bdx_tx_cleanup()
1738 		WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,  in bdx_tx_cleanup()
1812 	WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);  in bdx_tx_push_desc()
2218 	WRITE_REG(priv, regRDINTCM0, rdintcm);  in bdx_set_coalesce()
2219 	WRITE_REG(priv, regTDINTCM0, tdintcm);  in bdx_set_coalesce()