Lines Matching refs:DMA_CONTROL
61 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
63 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
68 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
70 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
75 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
77 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
82 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
84 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
236 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
237 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
239 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); in dwmac_dma_flush_tx_fifo()