301 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_dma_tx_chan_op_mode()  local
307 		mtl_tx_op |= MTL_OP_MODE_TSF;  in dwmac4_dma_tx_chan_op_mode()
310 		mtl_tx_op &= ~MTL_OP_MODE_TSF;  in dwmac4_dma_tx_chan_op_mode()
311 		mtl_tx_op &= MTL_OP_MODE_TTC_MASK;  in dwmac4_dma_tx_chan_op_mode()
314 			mtl_tx_op |= MTL_OP_MODE_TTC_32;  in dwmac4_dma_tx_chan_op_mode()
316 			mtl_tx_op |= MTL_OP_MODE_TTC_64;  in dwmac4_dma_tx_chan_op_mode()
318 			mtl_tx_op |= MTL_OP_MODE_TTC_96;  in dwmac4_dma_tx_chan_op_mode()
320 			mtl_tx_op |= MTL_OP_MODE_TTC_128;  in dwmac4_dma_tx_chan_op_mode()
322 			mtl_tx_op |= MTL_OP_MODE_TTC_192;  in dwmac4_dma_tx_chan_op_mode()
324 			mtl_tx_op |= MTL_OP_MODE_TTC_256;  in dwmac4_dma_tx_chan_op_mode()
326 			mtl_tx_op |= MTL_OP_MODE_TTC_384;  in dwmac4_dma_tx_chan_op_mode()
328 			mtl_tx_op |= MTL_OP_MODE_TTC_512;  in dwmac4_dma_tx_chan_op_mode()
339 	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;  in dwmac4_dma_tx_chan_op_mode()
341 		mtl_tx_op |= MTL_OP_MODE_TXQEN;  in dwmac4_dma_tx_chan_op_mode()
343 		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;  in dwmac4_dma_tx_chan_op_mode()
344 	mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;  in dwmac4_dma_tx_chan_op_mode()
345 	mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;  in dwmac4_dma_tx_chan_op_mode()
347 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_dma_tx_chan_op_mode()
464 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_qmode()  local
466 	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;  in dwmac4_qmode()
468 		mtl_tx_op |= MTL_OP_MODE_TXQEN;  in dwmac4_qmode()
470 		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;  in dwmac4_qmode()
472 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_qmode()