56 	ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);  in ravb_modify()
91 		ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);  in ravb_set_rate_gbeth()
94 		ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);  in ravb_set_rate_gbeth()
97 		ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);  in ravb_set_rate_gbeth()
108 		ravb_write(ndev, GECMR_SPEED_100, GECMR);  in ravb_set_rate_rcar()
111 		ravb_write(ndev, GECMR_SPEED_1000, GECMR);  in ravb_set_rate_rcar()
521 	ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);  in ravb_emac_init_gbeth()
524 	ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |  in ravb_emac_init_gbeth()
531 	ravb_write(ndev,  in ravb_emac_init_gbeth()
534 	ravb_write(ndev, (ndev->dev_addr[4] << 8)  | (ndev->dev_addr[5]), MALR);  in ravb_emac_init_gbeth()
537 	ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);  in ravb_emac_init_gbeth()
538 	ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);  in ravb_emac_init_gbeth()
541 	ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);  in ravb_emac_init_gbeth()
545 		ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);  in ravb_emac_init_gbeth()
555 	ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);  in ravb_emac_init_rcar()
558 	ravb_write(ndev, ECMR_ZPF | ECMR_DM |  in ravb_emac_init_rcar()
565 	ravb_write(ndev,  in ravb_emac_init_rcar()
568 	ravb_write(ndev,  in ravb_emac_init_rcar()
572 	ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);  in ravb_emac_init_rcar()
575 	ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);  in ravb_emac_init_rcar()
599 	ravb_write(ndev, 0x60000000, RCR);  in ravb_dmac_init_gbeth()
602 	ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC);  in ravb_dmac_init_gbeth()
605 	ravb_write(ndev, 0x00222200, TGC);  in ravb_dmac_init_gbeth()
607 	ravb_write(ndev, 0, TCCR);  in ravb_dmac_init_gbeth()
610 	ravb_write(ndev, RIC0_FRE0, RIC0);  in ravb_dmac_init_gbeth()
612 	ravb_write(ndev, 0x0, RIC1);  in ravb_dmac_init_gbeth()
614 	ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);  in ravb_dmac_init_gbeth()
616 	ravb_write(ndev, TIC_FTE0, TIC);  in ravb_dmac_init_gbeth()
641 	ravb_write(ndev,  in ravb_dmac_init_rcar()
645 	ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);  in ravb_dmac_init_rcar()
648 	ravb_write(ndev, TCCR_TFEN, TCCR);  in ravb_dmac_init_rcar()
653 		ravb_write(ndev, 0, DIL);  in ravb_dmac_init_rcar()
655 		ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);  in ravb_dmac_init_rcar()
658 	ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);  in ravb_dmac_init_rcar()
660 	ravb_write(ndev, 0, RIC1);  in ravb_dmac_init_rcar()
662 	ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);  in ravb_dmac_init_rcar()
664 	ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);  in ravb_dmac_init_rcar()
1060 	ravb_write(ndev, ecsr, ECSR);	/* clear interrupt */  in ravb_emac_interrupt_unlocked()
1101 	ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);  in ravb_error_interrupt()
1104 		ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),  in ravb_error_interrupt()
1134 				ravb_write(ndev, ric0 & ~BIT(q), RIC0);  in ravb_queue_interrupt()
1135 				ravb_write(ndev, tic & ~BIT(q), TIC);  in ravb_queue_interrupt()
1137 				ravb_write(ndev, BIT(q), RID0);  in ravb_queue_interrupt()
1138 				ravb_write(ndev, BIT(q), TID);  in ravb_queue_interrupt()
1159 		ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);  in ravb_timestamp_interrupt()
1297 	ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);  in ravb_poll()
1306 	ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);  in ravb_poll()
1319 		ravb_write(ndev, mask, RIE0);  in ravb_poll()
1320 		ravb_write(ndev, mask, TIE);  in ravb_poll()
2095 		ravb_write(ndev, 0, TROCR);	/* (write clear) */  in ravb_get_stats()
2100 		ravb_write(ndev, 0, CXR41);	/* (write clear) */  in ravb_get_stats()
2102 		ravb_write(ndev, 0, CXR42);	/* (write clear) */  in ravb_get_stats()
2158 	ravb_write(ndev, 0, RIC0);  in ravb_close()
2159 	ravb_write(ndev, 0, RIC2);  in ravb_close()
2160 	ravb_write(ndev, 0, TIC);  in ravb_close()
2553 	ravb_write(ndev, inc, GTI);  in ravb_set_gti()
2817 	ravb_write(ndev, priv->desc_bat_dma, DBAT);  in ravb_probe()
2905 	ravb_write(ndev, CCC_OPC_RESET, CCC);  in ravb_remove()
2926 	ravb_write(ndev, 0, RIC0);  in ravb_wol_setup()
2927 	ravb_write(ndev, 0, RIC2);  in ravb_wol_setup()
2928 	ravb_write(ndev, 0, TIC);  in ravb_wol_setup()
2935 	ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);  in ravb_wol_setup()
2991 		ravb_write(ndev, CCC_OPC_RESET, CCC);  in ravb_resume()
3015 	ravb_write(ndev, priv->desc_bat_dma, DBAT);  in ravb_resume()