44 	.pdma = {
87 	.pdma = {
103 	.pdma = {
738 	val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);  in mtk_rx_irq_disable()
739 	mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);  in mtk_rx_irq_disable()
749 	val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);  in mtk_rx_irq_enable()
750 	mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);  in mtk_rx_irq_enable()
2176 			reg_map->pdma.irq_status);  in mtk_napi_rx()
2183 				 mtk_r32(eth, reg_map->pdma.irq_status),  in mtk_napi_rx()
2184 				 mtk_r32(eth, reg_map->pdma.irq_mask));  in mtk_napi_rx()
2190 	} while (mtk_r32(eth, reg_map->pdma.irq_status) &  in mtk_napi_rx()
2273 		mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);  in mtk_tx_alloc()
2411 		ring->crx_idx_reg = reg_map->pdma.pcrx_ptr +  in mtk_rx_alloc()
2427 			reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET);  in mtk_rx_alloc()
2429 			reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);  in mtk_rx_alloc()
2431 			reg_map->pdma.rst_idx);  in mtk_rx_alloc()
2751 		reg = eth->soc->reg_map->pdma.glo_cfg;  in mtk_dma_busy_wait()
2886 	if (mtk_r32(eth, reg_map->pdma.irq_mask) &  in mtk_handle_irq()
2888 		if (mtk_r32(eth, reg_map->pdma.irq_status) &  in mtk_handle_irq()
2943 			reg_map->pdma.glo_cfg);  in mtk_start_dma()
2947 			reg_map->pdma.glo_cfg);  in mtk_start_dma()
3078 	mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg);  in mtk_stop()
3182 	val = mtk_r32(eth, reg_map->pdma.delay_irq);  in mtk_dim_rx()
3192 	mtk_w32(eth, val, reg_map->pdma.delay_irq);  in mtk_dim_rx()
3213 	val = mtk_r32(eth, reg_map->pdma.delay_irq);  in mtk_dim_tx()
3223 	mtk_w32(eth, val, reg_map->pdma.delay_irq);  in mtk_dim_tx()
3360 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);  in mtk_hw_init()
3361 	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);  in mtk_hw_init()