Lines Matching refs:mcs_reg_write
266 mcs_reg_write(mcs, reg, BIT_ULL(0)); in mcs_clear_stats()
289 mcs_reg_write(mcs, reg, 0x0); in mcs_clear_stats()
340 mcs_reg_write(mcs, reg, next_pn); in mcs_pn_table_write()
355 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
359 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
369 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_rx_sa_mem_map_write()
380 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
385 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
403 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_sc_cam_entry()
408 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(0, sc_id), sci); in mcs_rx_sc_cam_write()
409 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(1, sc_id), secy); in mcs_rx_sc_cam_write()
423 mcs_reg_write(mcs, reg, plcy); in mcs_secy_plcy_write()
426 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_1X(secy_id), 0x0ull); in mcs_secy_plcy_write()
441 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_flowid_secy_map()
464 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_flowid_entry()
475 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
477 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
482 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
484 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
499 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
503 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
589 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
597 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
617 mcs_reg_write(mcs, reg, req->data0); in mcs_ctrlpktrule_write()
627 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
636 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
638 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
641 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
643 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
655 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
657 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
659 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
662 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
664 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
666 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
677 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
685 mcs_reg_write(mcs, reg, enb); in mcs_ctrlpktrule_write()
992 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1C, BIT_ULL(0)); in mcs_ip_intr_handler()
993 mcs_reg_write(mcs, MCSX_IP_INT, BIT_ULL(0)); in mcs_ip_intr_handler()
1010 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT, cpm_intr); in mcs_ip_intr_handler()
1034 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT, cpm_intr); in mcs_ip_intr_handler()
1043 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1044 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT, bbe_intr); in mcs_ip_intr_handler()
1053 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1054 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT, bbe_intr); in mcs_ip_intr_handler()
1063 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1064 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT, pab_intr); in mcs_ip_intr_handler()
1073 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1074 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT, pab_intr); in mcs_ip_intr_handler()
1078 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0)); in mcs_ip_intr_handler()
1167 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0)); in mcs_register_interrupts()
1170 mcs_reg_write(mcs, MCSX_TOP_SLAVE_INT_SUM_ENB, in mcs_register_interrupts()
1175 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT_ENB, 0x7ULL); in mcs_register_interrupts()
1176 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT_ENB, 0x7FULL); in mcs_register_interrupts()
1178 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_ENB, 0xff); in mcs_register_interrupts()
1179 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_ENB, 0xff); in mcs_register_interrupts()
1181 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_ENB, 0xff); in mcs_register_interrupts()
1182 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_ENB, 0xff); in mcs_register_interrupts()
1234 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id), in mcs_set_port_cfg()
1243 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id), val); in mcs_set_port_cfg()
1244 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id), in mcs_set_port_cfg()
1253 mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION, val); in mcs_set_port_cfg()
1257 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id), val); in mcs_set_port_cfg()
1321 mcs_reg_write(mcs, reg, reset & 0x1); in mcs_reset_port()
1330 mcs_reg_write(mcs, reg, (u64)mode); in mcs_set_lmac_mode()
1342 mcs_reg_write(mcs, reg, pn->threshold); in mcs_pn_threshold_set()
1353 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1357 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1363 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1367 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1376 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()
1380 mcs_reg_write(mcs, reg, 0xe000e); in mcs_lmac_init()
1385 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()
1402 mcs_reg_write(mcs, MCSX_LINK_LMACX_CFG(lmac), cfg); in mcs_set_lmac_channels()
1417 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_x2p_calibration()
1439 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, mcs_reg_read(mcs, MCSX_MIL_GLOBAL) & ~BIT_ULL(5)); in mcs_x2p_calibration()
1454 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_set_external_bypass()
1463 mcs_reg_write(mcs, MCSX_CSE_RX_SLAVE_STATS_CLEAR, 0x1F); in mcs_global_cfg()
1464 mcs_reg_write(mcs, MCSX_CSE_TX_SLAVE_STATS_CLEAR, 0x1F); in mcs_global_cfg()
1468 mcs_reg_write(mcs, MCSX_IP_MODE, BIT_ULL(3)); in mcs_global_cfg()
1472 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_ENTRY, 0xe4); in mcs_global_cfg()
1473 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_LEN, 4); in mcs_global_cfg()