90 		wr32(&pf->hw, GLINT_DYN_CTL(i), GLINT_DYN_CTL_CLEARPBA_M);  in ice_free_vf_res()
116 	wr32(hw, VPINT_ALLOC(vf->vf_id), 0);  in ice_dis_vf_mappings()
117 	wr32(hw, VPINT_ALLOC_PCI(vf->vf_id), 0);  in ice_dis_vf_mappings()
128 		wr32(hw, GLINT_VECT2FUNC(v), reg);  in ice_dis_vf_mappings()
132 		wr32(hw, VPLAN_TX_QBASE(vf->vf_id), 0);  in ice_dis_vf_mappings()
137 		wr32(hw, VPLAN_RX_QBASE(vf->vf_id), 0);  in ice_dis_vf_mappings()
218 			wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));  in ice_free_vfs()
317 	wr32(hw, VPINT_ALLOC(vf->vf_id), reg);  in ice_ena_vf_msix_mappings()
323 	wr32(hw, VPINT_ALLOC_PCI(vf->vf_id), reg);  in ice_ena_vf_msix_mappings()
331 		wr32(hw, GLINT_VECT2FUNC(v), reg);  in ice_ena_vf_msix_mappings()
335 	wr32(hw, VPINT_MBX_CTL(device_based_vf_id), VPINT_MBX_CTL_CAUSE_ENA_M);  in ice_ena_vf_msix_mappings()
355 	wr32(hw, VPLAN_TXQ_MAPENA(vf->vf_id), VPLAN_TXQ_MAPENA_TX_ENA_M);  in ice_ena_vf_q_mappings()
367 		wr32(hw, VPLAN_TX_QBASE(vf->vf_id), reg);  in ice_ena_vf_q_mappings()
373 	wr32(hw, VPLAN_RXQ_MAPENA(vf->vf_id), VPLAN_RXQ_MAPENA_RX_ENA_M);  in ice_ena_vf_q_mappings()
385 		wr32(hw, VPLAN_RX_QBASE(vf->vf_id), reg);  in ice_ena_vf_q_mappings()
665 		wr32(hw, VFGEN_RSTAT(vf->vf_id), VIRTCHNL_VFR_VFACTIVE);  in ice_start_vfs()
707 	wr32(&pf->hw, VF_MBX_ARQLEN(vf->vf_id), 0);  in ice_sriov_clear_mbx_register()
708 	wr32(&pf->hw, VF_MBX_ATQLEN(vf->vf_id), 0);  in ice_sriov_clear_mbx_register()
737 		wr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg);  in ice_sriov_trigger_reset_register()
743 	wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));  in ice_sriov_trigger_reset_register()
746 	wr32(hw, PF_PCI_CIAA,  in ice_sriov_trigger_reset_register()
797 	wr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg);  in ice_sriov_clear_reset_trigger()
832 	wr32(&vf->pf->hw, VFGEN_RSTAT(vf->vf_id), VIRTCHNL_VFR_VFACTIVE);  in ice_sriov_post_vsi_rebuild()
920 	wr32(hw, GLINT_DYN_CTL(pf->oicr_idx),  in ice_ena_vfs()