38 int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,  in hinic_msix_attr_set()  argument
45 	if (!VALID_MSIX_IDX(&hwif->attr, msix_index))  in hinic_msix_attr_set()
56 	hinic_hwif_write_reg(hwif, addr, msix_ctrl);  in hinic_msix_attr_set()
67 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index)  in hinic_msix_attr_cnt_clear()  argument
71 	if (!VALID_MSIX_IDX(&hwif->attr, msix_index))  in hinic_msix_attr_cnt_clear()
77 	hinic_hwif_write_reg(hwif, addr, msix_ctrl);  in hinic_msix_attr_cnt_clear()
86 void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action)  in hinic_set_pf_action()  argument
90 	if (HINIC_IS_VF(hwif))  in hinic_set_pf_action()
93 	attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR);  in hinic_set_pf_action()
97 	hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR, attr5);  in hinic_set_pf_action()
100 enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif)  in hinic_outbound_state_get()  argument
102 	u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);  in hinic_outbound_state_get()
107 void hinic_outbound_state_set(struct hinic_hwif *hwif,  in hinic_outbound_state_set()  argument
110 	u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);  in hinic_outbound_state_set()
115 	hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4);  in hinic_outbound_state_set()
118 enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif)  in hinic_db_state_get()  argument
120 	u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);  in hinic_db_state_get()
125 void hinic_db_state_set(struct hinic_hwif *hwif,  in hinic_db_state_set()  argument
128 	u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);  in hinic_db_state_set()
133 	hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4);  in hinic_db_state_set()
136 void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx,  in hinic_set_msix_state()  argument
143 	mask_bits = readl(hwif->intr_regs_base + offset);  in hinic_set_msix_state()
149 	writel(mask_bits, hwif->intr_regs_base + offset);  in hinic_set_msix_state()
158 static int hwif_ready(struct hinic_hwif *hwif)  in hwif_ready()  argument
163 	attr1  = hinic_hwif_read_reg(hwif, addr);  in hwif_ready()
168 	if (HINIC_IS_VF(hwif)) {  in hwif_ready()
176 static int wait_hwif_ready(struct hinic_hwif *hwif)  in wait_hwif_ready()  argument
181 		if (!hwif_ready(hwif))  in wait_hwif_ready()
188 	dev_err(&hwif->pdev->dev, "Wait for hwif timeout\n");  in wait_hwif_ready()
200 static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1,  in set_hwif_attr()  argument
203 	hwif->attr.func_idx     = HINIC_FA0_GET(attr0, FUNC_IDX);  in set_hwif_attr()
204 	hwif->attr.pf_idx       = HINIC_FA0_GET(attr0, PF_IDX);  in set_hwif_attr()
205 	hwif->attr.pci_intf_idx = HINIC_FA0_GET(attr0, PCI_INTF_IDX);  in set_hwif_attr()
206 	hwif->attr.func_type    = HINIC_FA0_GET(attr0, FUNC_TYPE);  in set_hwif_attr()
208 	hwif->attr.num_aeqs = BIT(HINIC_FA1_GET(attr1, AEQS_PER_FUNC));  in set_hwif_attr()
209 	hwif->attr.num_ceqs = BIT(HINIC_FA1_GET(attr1, CEQS_PER_FUNC));  in set_hwif_attr()
210 	hwif->attr.num_irqs = BIT(HINIC_FA1_GET(attr1, IRQS_PER_FUNC));  in set_hwif_attr()
211 	hwif->attr.num_dma_attr = BIT(HINIC_FA1_GET(attr1, DMA_ATTR_PER_FUNC));  in set_hwif_attr()
212 	hwif->attr.global_vf_id_of_pf = HINIC_FA2_GET(attr2,  in set_hwif_attr()
220 static void read_hwif_attr(struct hinic_hwif *hwif)  in read_hwif_attr()  argument
225 	attr0  = hinic_hwif_read_reg(hwif, addr);  in read_hwif_attr()
228 	attr1  = hinic_hwif_read_reg(hwif, addr);  in read_hwif_attr()
231 	attr2  = hinic_hwif_read_reg(hwif, addr);  in read_hwif_attr()
233 	set_hwif_attr(hwif, attr0, attr1, attr2);  in read_hwif_attr()
240 static void set_ppf(struct hinic_hwif *hwif)  in set_ppf()  argument
242 	struct hinic_func_attr *attr = &hwif->attr;  in set_ppf()
246 	addr = HINIC_CSR_PPF_ELECTION_ADDR(HINIC_HWIF_PCI_INTF(hwif));  in set_ppf()
248 	val = hinic_hwif_read_reg(hwif, addr);  in set_ppf()
251 	ppf_election = HINIC_PPF_ELECTION_SET(HINIC_HWIF_FUNC_IDX(hwif), IDX);  in set_ppf()
254 	hinic_hwif_write_reg(hwif, addr, val);  in set_ppf()
257 	val = hinic_hwif_read_reg(hwif, addr);  in set_ppf()
260 	if (attr->ppf_idx == HINIC_HWIF_FUNC_IDX(hwif))  in set_ppf()
274 static void set_dma_attr(struct hinic_hwif *hwif, u32 entry_idx,  in set_dma_attr()  argument
284 	val = hinic_hwif_read_reg(hwif, addr);  in set_dma_attr()
298 	hinic_hwif_write_reg(hwif, addr, val);  in set_dma_attr()
305 static void dma_attr_init(struct hinic_hwif *hwif)  in dma_attr_init()  argument
307 	set_dma_attr(hwif, PCIE_ATTR_ENTRY, HINIC_PCIE_ST_DISABLE,  in dma_attr_init()
312 u16 hinic_glb_pf_vf_offset(struct hinic_hwif *hwif)  in hinic_glb_pf_vf_offset()  argument
314 	if (!hwif)  in hinic_glb_pf_vf_offset()
317 	return hwif->attr.global_vf_id_of_pf;  in hinic_glb_pf_vf_offset()
320 u16 hinic_global_func_id_hw(struct hinic_hwif *hwif)  in hinic_global_func_id_hw()  argument
325 	attr0  = hinic_hwif_read_reg(hwif, addr);  in hinic_global_func_id_hw()
330 u16 hinic_pf_id_of_vf_hw(struct hinic_hwif *hwif)  in hinic_pf_id_of_vf_hw()  argument
335 	attr0  = hinic_hwif_read_reg(hwif, addr);  in hinic_pf_id_of_vf_hw()
340 static void __print_selftest_reg(struct hinic_hwif *hwif)  in __print_selftest_reg()  argument
345 	attr1  = hinic_hwif_read_reg(hwif, addr);  in __print_selftest_reg()
348 		dev_err(&hwif->pdev->dev, "PCIE is link down\n");  in __print_selftest_reg()
353 	attr0  = hinic_hwif_read_reg(hwif, addr);  in __print_selftest_reg()
356 		dev_err(&hwif->pdev->dev, "Selftest reg: 0x%08x\n",  in __print_selftest_reg()
357 			hinic_hwif_read_reg(hwif, HINIC_SELFTEST_RESULT));  in __print_selftest_reg()
367 int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev)  in hinic_init_hwif()  argument
371 	hwif->pdev = pdev;  in hinic_init_hwif()
373 	hwif->cfg_regs_bar = pci_ioremap_bar(pdev, HINIC_PCI_CFG_REGS_BAR);  in hinic_init_hwif()
374 	if (!hwif->cfg_regs_bar) {  in hinic_init_hwif()
379 	hwif->intr_regs_base = pci_ioremap_bar(pdev, HINIC_PCI_INTR_REGS_BAR);  in hinic_init_hwif()
380 	if (!hwif->intr_regs_base) {  in hinic_init_hwif()
386 	err = wait_hwif_ready(hwif);  in hinic_init_hwif()
389 		__print_selftest_reg(hwif);  in hinic_init_hwif()
393 	read_hwif_attr(hwif);  in hinic_init_hwif()
395 	if (HINIC_IS_PF(hwif))  in hinic_init_hwif()
396 		set_ppf(hwif);  in hinic_init_hwif()
399 	dma_attr_init(hwif);  in hinic_init_hwif()
403 	iounmap(hwif->intr_regs_base);  in hinic_init_hwif()
406 	iounmap(hwif->cfg_regs_bar);  in hinic_init_hwif()
415 void hinic_free_hwif(struct hinic_hwif *hwif)  in hinic_free_hwif()  argument
417 	iounmap(hwif->intr_regs_base);  in hinic_free_hwif()
418 	iounmap(hwif->cfg_regs_bar);  in hinic_free_hwif()