Lines Matching defs:fman_dma_regs

429 struct fman_dma_regs {  struct
430 	u32 fmdmsr;	/* FM DMA status register 0x00 */
431 	u32 fmdmmr;	/* FM DMA mode register 0x04 */
432 	u32 fmdmtr;	/* FM DMA bus threshold register 0x08 */
433 	u32 fmdmhy;	/* FM DMA bus hysteresis register 0x0c */
434 	u32 fmdmsetr;	/* FM DMA SOS emergency Threshold Register 0x10 */
435 	u32 fmdmtah;	/* FM DMA transfer bus address high reg 0x14 */
436 	u32 fmdmtal;	/* FM DMA transfer bus address low reg 0x18 */
437 	u32 fmdmtcid;	/* FM DMA transfer bus communication ID reg 0x1c */
438 	u32 fmdmra;	/* FM DMA bus internal ram address register 0x20 */
439 	u32 fmdmrd;	/* FM DMA bus internal ram data register 0x24 */
440 	u32 fmdmwcr;	/* FM DMA CAM watchdog counter value 0x28 */
441 	u32 fmdmebcr;	/* FM DMA CAM base in MURAM register 0x2c */
442 	u32 fmdmccqdr;	/* FM DMA CAM and CMD Queue Debug reg 0x30 */
443 	u32 fmdmccqvr1;	/* FM DMA CAM and CMD Queue Value reg #1 0x34 */
444 	u32 fmdmccqvr2;	/* FM DMA CAM and CMD Queue Value reg #2 0x38 */
445 	u32 fmdmcqvr3;	/* FM DMA CMD Queue Value register #3 0x3c */
446 	u32 fmdmcqvr4;	/* FM DMA CMD Queue Value register #4 0x40 */
447 	u32 fmdmcqvr5;	/* FM DMA CMD Queue Value register #5 0x44 */
448 	u32 fmdmsefrc;	/* FM DMA Semaphore Entry Full Reject Cntr 0x48 */
449 	u32 fmdmsqfrc;	/* FM DMA Semaphore Queue Full Reject Cntr 0x4c */
450 	u32 fmdmssrc;	/* FM DMA Semaphore SYNC Reject Counter 0x50 */
451 	u32 fmdmdcr;	/* FM DMA Debug Counter 0x54 */
452 	u32 fmdmemsr;	/* FM DMA Emergency Smoother Register 0x58 */
453 	u32 res005c;	/* 0x5c */
454 	u32 fmdmplr[FMAN_LIODN_TBL / 2];	/* DMA LIODN regs 0x60-0xdf */
455 	u32 res00e0[0x400 - 56];