182 #define wrl(ep, off, val)	__raw_writel((val), (ep)->base_addr + (off))  macro
190 	wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);  in ep93xx_mdio_read()
213 	wrl(ep, REG_MIIDATA, data);  in ep93xx_mdio_write()
214 	wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);  in ep93xx_mdio_write()
318 		wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);  in ep93xx_poll()
361 	wrl(ep, REG_TXDENQ, 1);  in ep93xx_xmit()
432 			wrl(ep, REG_INTEN, REG_INTEN_TX);  in ep93xx_irq()
537 	wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);  in ep93xx_start_hw()
549 	wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));  in ep93xx_start_hw()
553 		wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));  in ep93xx_start_hw()
557 	wrl(ep, REG_RXDQBADD, addr);  in ep93xx_start_hw()
558 	wrl(ep, REG_RXDCURADD, addr);  in ep93xx_start_hw()
563 	wrl(ep, REG_RXSTSQBADD, addr);  in ep93xx_start_hw()
564 	wrl(ep, REG_RXSTSQCURADD, addr);  in ep93xx_start_hw()
569 	wrl(ep, REG_TXDQBADD, addr);  in ep93xx_start_hw()
570 	wrl(ep, REG_TXDQCURADD, addr);  in ep93xx_start_hw()
575 	wrl(ep, REG_TXSTSQBADD, addr);  in ep93xx_start_hw()
576 	wrl(ep, REG_TXSTSQCURADD, addr);  in ep93xx_start_hw()
579 	wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);  in ep93xx_start_hw()
580 	wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);  in ep93xx_start_hw()
581 	wrl(ep, REG_GIINTMSK, 0);  in ep93xx_start_hw()
594 	wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);  in ep93xx_start_hw()
595 	wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);  in ep93xx_start_hw()
603 	wrl(ep, REG_AFP, 0);  in ep93xx_start_hw()
605 	wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);  in ep93xx_start_hw()
607 	wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);  in ep93xx_start_hw()
608 	wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);  in ep93xx_start_hw()
618 	wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);  in ep93xx_stop_hw()
660 	wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);  in ep93xx_open()
674 	wrl(ep, REG_GIINTMSK, 0);  in ep93xx_close()