Lines Matching refs:t4_write_reg
97 t4_write_reg(adapter, addr, v | val); in t4_set_reg_field()
118 t4_write_reg(adap, addr_reg, start_idx); in t4_read_indirect()
141 t4_write_reg(adap, addr_reg, start_idx++); in t4_write_indirect()
142 t4_write_reg(adap, data_reg, *vals++); in t4_write_indirect()
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req); in t4_hw_pci_read_cfg4()
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()
383 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); in t4_wr_mbox_meat_timeout()
404 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout()
418 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout()
553 t4_write_reg(adap, in t4_memory_update_win()
592 t4_write_reg(adap, addr, in t4_memory_rw_residual()
696 t4_write_reg(adap, mem_base + offset, in t4_memory_rw()
814 t4_write_reg(adap, in t4_setup_memwin()
2936 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | in sf1_read()
2963 t4_write_reg(adapter, SF_DATA_A, val); in sf1_write()
2964 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | in sf1_write()
3025 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ in t4_read_flash()
3080 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ in t4_write_flash()
3097 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ in t4_write_flash()
3575 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ in t4_flash_erase_sectors()
3873 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); in t4_cim_read_pif_la()
3885 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) | in t4_cim_read_pif_la()
3895 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); in t4_cim_read_pif_la()
3905 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); in t4_cim_read_ma_la()
3910 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) | in t4_cim_read_ma_la()
3916 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); in t4_cim_read_ma_la()
3926 t4_write_reg(adap, ULP_RX_LA_CTL_A, i); in t4_ulprx_read_la()
3928 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j); in t4_ulprx_read_la()
4307 t4_write_reg(adapter, reg, status); in t4_handle_intr_status()
4522 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F | in sge_intr_handler()
4601 t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A, in cim_intr_handler()
4821 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0); in mps_intr_handler()
4864 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M)); in mem_intr_handler()
4874 t4_write_reg(adapter, addr, v); in mem_intr_handler()
4903 t4_write_reg(adap, MA_INT_CAUSE_A, status); in ma_intr_handler()
4964 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v); in xgmac_intr_handler()
5056 t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK); in t4_slow_intr_handler()
5083 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F | in t4_intr_enable()
5090 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK); in t4_intr_enable()
5113 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0); in t4_intr_disable()
5249 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row); in rd_rss_row()
5485 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, in t4_write_rss_key()
5489 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, in t4_write_rss_key()
5539 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt); in t4_read_rss_vf_config()
5742 t4_write_reg(adap, TP_MTU_TABLE_A, in t4_read_mtu_tbl()
5765 t4_write_reg(adap, TP_CCTRL_TABLE_A, in t4_read_cong_tbl()
5784 t4_write_reg(adap, TP_PIO_ADDR_A, addr); in t4_tp_wr_bits_indirect()
5786 t4_write_reg(adap, TP_PIO_DATA_A, val); in t4_tp_wr_bits_indirect()
5865 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) | in t4_load_mtus()
5874 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) | in t4_load_mtus()
5944 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); in t4_set_trace_filter()
5971 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); in t4_set_trace_filter()
5978 t4_write_reg(adap, data_reg, tp->data[i]); in t4_set_trace_filter()
5979 t4_write_reg(adap, mask_reg, ~tp->mask[i]); in t4_set_trace_filter()
5981 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst, in t4_set_trace_filter()
5984 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, in t4_set_trace_filter()
6051 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1); in t4_pmtx_get_stats()
6078 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1); in t4_pmrx_get_stats()
7114 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F); in t4_fw_restart()
7279 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A, in t4_fixup_host_params()
7397 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size); in t4_fixup_host_params()
7398 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A, in t4_fixup_host_params()
7401 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A, in t4_fixup_host_params()
7405 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); in t4_fixup_host_params()
8973 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */ in t4_get_flash_params()
9210 t4_write_reg(adapter, DBG_GPIO_EN_A, 0); in t4_shutdown_adapter()
9216 t4_write_reg(adapter, a_port_cfg, in t4_shutdown_adapter()
9748 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F | in t4_read_cimq_cfg()
9757 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | in t4_read_cimq_cfg()
9796 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) | in t4_read_cim_ibq()
9804 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0); in t4_read_cim_ibq()
9829 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | in t4_read_cim_obq()
9839 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) | in t4_read_cim_obq()
9847 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0); in t4_read_cim_obq()
9869 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr); in t4_cim_read()
9896 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++); in t4_cim_write()
9897 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F); in t4_cim_write()
9996 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, in t4_tp_read_la()
10012 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val); in t4_tp_read_la()
10022 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, in t4_tp_read_la()
10083 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13); in t4_idma_monitor()
10136 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0); in t4_idma_monitor()
10140 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11); in t4_idma_monitor()
10265 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i); in t4_read_pace_tbl()
10364 t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype)); in t4_sge_ctxt_rd_bd()