156 	if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)  in t4_hw_pci_read_cfg4()
836 	case CHELSIO_T5:  in t4_get_regs_len()
2654 	case CHELSIO_T5:  in t4_get_regs()
3385 	case CHELSIO_T5:  in t4_check_fw_version()
4499 	if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {  in sge_intr_handler()
4511 	if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)  in sge_intr_handler()
4738 				  (chip <= CHELSIO_T5) ?  in le_intr_handler()
5078 	u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?  in t4_intr_enable()
5081 	if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)  in t4_intr_enable()
5110 	pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?  in t4_intr_disable()
5119 	if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)  in t4_chip_rss_size()
5477 	if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&  in t4_write_rss_key()
5526 	if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {  in t4_read_rss_vf_config()
6110 	case CHELSIO_T5:  in compute_mps_bg_map()
6250 	case CHELSIO_T5:  in t4_get_tp_ch_map()
6377 	if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {  in t4_get_port_stats()
6411 	if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {  in t4_get_port_stats()
6722 	case CHELSIO_T5:  in t4_sge_decode_idma_state()
7235 	if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)  in t4_fl_pkt_align()
8174 								     CHELSIO_T5)  in t4_change_mac()
9146 	case CHELSIO_T5:  in t4_prep_adapter()
9147 		adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);  in t4_prep_adapter()
9468 	if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {  in t4_init_tp_params()