57 	t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |  in xaui_serdes_reset()
102 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);  in t3_mac_reset()
139 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);  in t3_mac_reset()
167 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);  in t3b2_mac_reset()
171 	t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);  in t3b2_mac_reset()
177 	t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);  in t3b2_mac_reset()
178 	t3_write_reg(adap, A_TP_PIO_DATA, 0xc0000011);  in t3b2_mac_reset()
189 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0);  in t3b2_mac_reset()
199 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);  in t3b2_mac_reset()
205 	t3_write_reg(adap, A_XGM_RX_CFG + oft,  in t3b2_mac_reset()
210 	t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);  in t3b2_mac_reset()
211 	t3_write_reg(adap, A_TP_PIO_DATA, store);  in t3b2_mac_reset()
238 	t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1 + oft, addr_lo);  in set_addr_filter()
239 	t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi);  in set_addr_filter()
270 		t3_write_reg(mac->adapter, reg, v);  in t3_mac_disable_exact_filters()
281 		t3_write_reg(mac->adapter, reg, v);  in t3_mac_enable_exact_filters()
309 	t3_write_reg(adap, A_XGM_RX_CFG + oft, val);  in t3_mac_set_rx_mode()
332 	t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);  in t3_mac_set_rx_mode()
333 	t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);  in t3_mac_set_rx_mode()
362 	t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);  in t3_mac_set_mtu()
377 			t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);  in t3_mac_set_mtu()
384 		t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);  in t3_mac_set_mtu()
404 	t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);  in t3_mac_set_mtu()
420 		t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,  in t3_mac_set_mtu()
423 	t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,  in t3_mac_set_mtu()
460 	t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);  in t3_mac_set_speed_duplex_fc()
475 		t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);  in t3_mac_enable()
476 		t3_write_reg(adap, A_TP_PIO_DATA,  in t3_mac_enable()
479 		t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);  in t3_mac_enable()
483 		t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);  in t3_mac_enable()
485 		t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);  in t3_mac_enable()
502 		t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);  in t3_mac_enable()
511 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);  in t3_mac_disable()
520 		t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);  in t3_mac_disable()
527 		t3_write_reg(mac->adapter, A_XGM_RESET_CTRL + mac->offset, val);  in t3_mac_disable()
548 			t3_write_reg(adap, A_TP_PIO_ADDR,  in t3b2_mac_watchdog_task()
579 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);  in t3b2_mac_watchdog_task()
581 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);  in t3b2_mac_watchdog_task()
651 	t3_write_reg(mac->adapter, A_TP_MIB_INDEX, mac->offset ? 51 : 50);  in t3_mac_update_stats()