Lines Matching defs:pn
167 #define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */ argument
168 #define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */ argument
169 #define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */ argument
174 #define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */ argument
175 #define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */ argument
176 #define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */ argument
177 #define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */ argument
178 #define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */ argument
179 #define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */ argument
180 #define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */ argument
181 #define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */ argument
182 #define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */ argument
183 #define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */ argument
184 #define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */ argument
185 #define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */ argument
186 #define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */ argument
187 #define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */ argument
188 #define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */ argument
189 #define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */ argument
190 #define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */ argument
191 #define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */ argument
192 #define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */ argument
193 #define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */ argument
271 #define REG_RX_OK_BYTES(pn) CRA(0x4,pn,RxOkBytes) argument
272 #define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,RxBadBytes) argument
273 #define REG_TX_OK_BYTES(pn) CRA(0x4,pn,TxOkBytes) argument