Lines Matching refs:oct
31 static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct) in lio_cn68xx_set_dpi_regs() argument
36 lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL); in lio_cn68xx_set_dpi_regs()
37 dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n", in lio_cn68xx_set_dpi_regs()
38 lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL)); in lio_cn68xx_set_dpi_regs()
45 lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i)); in lio_cn68xx_set_dpi_regs()
46 lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i)); in lio_cn68xx_set_dpi_regs()
47 dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i, in lio_cn68xx_set_dpi_regs()
48 lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i))); in lio_cn68xx_set_dpi_regs()
55 lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL); in lio_cn68xx_set_dpi_regs()
56 dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n", in lio_cn68xx_set_dpi_regs()
57 lio_pci_readq(oct, CN6XXX_DPI_CTL)); in lio_cn68xx_set_dpi_regs()
60 static int lio_cn68xx_soft_reset(struct octeon_device *oct) in lio_cn68xx_soft_reset() argument
62 lio_cn6xxx_soft_reset(oct); in lio_cn68xx_soft_reset()
63 lio_cn68xx_set_dpi_regs(oct); in lio_cn68xx_soft_reset()
68 static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct) in lio_cn68xx_setup_pkt_ctl_regs() argument
70 struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip; in lio_cn68xx_setup_pkt_ctl_regs()
73 pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL); in lio_cn68xx_setup_pkt_ctl_regs()
76 max_oqs = CFG_GET_OQ_MAX_Q(CHIP_CONF(oct, cn6xxx)); in lio_cn68xx_setup_pkt_ctl_regs()
77 tx_pipe = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE); in lio_cn68xx_setup_pkt_ctl_regs()
80 octeon_write_csr64(oct, CN68XX_SLI_TX_PIPE, tx_pipe); in lio_cn68xx_setup_pkt_ctl_regs()
87 octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl); in lio_cn68xx_setup_pkt_ctl_regs()
90 static int lio_cn68xx_setup_device_regs(struct octeon_device *oct) in lio_cn68xx_setup_device_regs() argument
92 lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT); in lio_cn68xx_setup_device_regs()
93 lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_256B); in lio_cn68xx_setup_device_regs()
94 lio_cn6xxx_enable_error_reporting(oct); in lio_cn68xx_setup_device_regs()
96 lio_cn6xxx_setup_global_input_regs(oct); in lio_cn68xx_setup_device_regs()
97 lio_cn68xx_setup_pkt_ctl_regs(oct); in lio_cn68xx_setup_device_regs()
98 lio_cn6xxx_setup_global_output_regs(oct); in lio_cn68xx_setup_device_regs()
103 octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL); in lio_cn68xx_setup_device_regs()
108 static inline void lio_cn68xx_vendor_message_fix(struct octeon_device *oct) in lio_cn68xx_vendor_message_fix() argument
113 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, &val); in lio_cn68xx_vendor_message_fix()
115 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, val); in lio_cn68xx_vendor_message_fix()
118 static int lio_is_210nv(struct octeon_device *oct) in lio_is_210nv() argument
120 u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG); in lio_is_210nv()
125 int lio_setup_cn68xx_octeon_device(struct octeon_device *oct) in lio_setup_cn68xx_octeon_device() argument
127 struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip; in lio_setup_cn68xx_octeon_device()
130 if (octeon_map_pci_barx(oct, 0, 0)) in lio_setup_cn68xx_octeon_device()
133 if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) { in lio_setup_cn68xx_octeon_device()
134 dev_err(&oct->pci_dev->dev, "%s CN68XX BAR1 map failed\n", in lio_setup_cn68xx_octeon_device()
136 octeon_unmap_pci_barx(oct, 0); in lio_setup_cn68xx_octeon_device()
142 oct->fn_list.setup_iq_regs = lio_cn6xxx_setup_iq_regs; in lio_setup_cn68xx_octeon_device()
143 oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs; in lio_setup_cn68xx_octeon_device()
145 oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs; in lio_setup_cn68xx_octeon_device()
146 oct->fn_list.soft_reset = lio_cn68xx_soft_reset; in lio_setup_cn68xx_octeon_device()
147 oct->fn_list.setup_device_regs = lio_cn68xx_setup_device_regs; in lio_setup_cn68xx_octeon_device()
148 oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index; in lio_setup_cn68xx_octeon_device()
150 oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup; in lio_setup_cn68xx_octeon_device()
151 oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write; in lio_setup_cn68xx_octeon_device()
152 oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read; in lio_setup_cn68xx_octeon_device()
154 oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt; in lio_setup_cn68xx_octeon_device()
155 oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt; in lio_setup_cn68xx_octeon_device()
157 oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues; in lio_setup_cn68xx_octeon_device()
158 oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues; in lio_setup_cn68xx_octeon_device()
160 lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list); in lio_setup_cn68xx_octeon_device()
163 if (lio_is_210nv(oct)) in lio_setup_cn68xx_octeon_device()
167 oct_get_config_info(oct, card_type); in lio_setup_cn68xx_octeon_device()
169 dev_err(&oct->pci_dev->dev, "%s No Config found for CN68XX %s\n", in lio_setup_cn68xx_octeon_device()
173 octeon_unmap_pci_barx(oct, 0); in lio_setup_cn68xx_octeon_device()
174 octeon_unmap_pci_barx(oct, 1); in lio_setup_cn68xx_octeon_device()
178 oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct); in lio_setup_cn68xx_octeon_device()
180 lio_cn68xx_vendor_message_fix(oct); in lio_setup_cn68xx_octeon_device()