633 				data[i] = REG_RD(bp, src_addr + i*4);  in bnx2x_read_dmae()
741 				regs[j] = REG_RD(bp, bar_storm_intmem[storm] +  in bnx2x_mc_assert()
793 	val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);  in bnx2x_fw_dump_lvl()
794 	if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))  in bnx2x_fw_dump_lvl()
814 	mark = REG_RD(bp, addr);  in bnx2x_fw_dump_lvl()
822 	mark = REG_RD(bp, addr);  in bnx2x_fw_dump_lvl()
835 			data[word] = htonl(REG_RD(bp, offset + 4*word));  in bnx2x_fw_dump_lvl()
843 			data[word] = htonl(REG_RD(bp, offset + 4*word));  in bnx2x_fw_dump_lvl()
859 	u32 val = REG_RD(bp, addr);  in bnx2x_hc_int_disable()
886 	if (REG_RD(bp, addr) != val)  in bnx2x_hc_int_disable()
892 	u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_igu_int_disable()
901 	if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)  in bnx2x_igu_int_disable()
957 				REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +  in bnx2x_panic_dump()
1054 			*(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +  in bnx2x_panic_dump()
1235 	crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);  in bnx2x_pbf_pN_buf_flushed()
1236 	crd = crd_start = REG_RD(bp, regs->crd);  in bnx2x_pbf_pN_buf_flushed()
1237 	init_crd = REG_RD(bp, regs->init_crd);  in bnx2x_pbf_pN_buf_flushed()
1247 			crd = REG_RD(bp, regs->crd);  in bnx2x_pbf_pN_buf_flushed()
1248 			crd_freed = REG_RD(bp, regs->crd_freed);  in bnx2x_pbf_pN_buf_flushed()
1270 	occup = to_free = REG_RD(bp, regs->lines_occup);  in bnx2x_pbf_pN_cmd_flushed()
1271 	freed = freed_start = REG_RD(bp, regs->lines_freed);  in bnx2x_pbf_pN_cmd_flushed()
1279 			occup = REG_RD(bp, regs->lines_occup);  in bnx2x_pbf_pN_cmd_flushed()
1280 			freed = REG_RD(bp, regs->lines_freed);  in bnx2x_pbf_pN_cmd_flushed()
1301 	while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)  in bnx2x_flr_clnup_reg_poll()
1410 	if (REG_RD(bp, comp_addr)) {  in bnx2x_send_final_clnup()
1426 		   (REG_RD(bp, comp_addr)));  in bnx2x_send_final_clnup()
1495 	val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);  in bnx2x_hw_enable_status()
1498 	val = REG_RD(bp, PBF_REG_DISABLE_PF);  in bnx2x_hw_enable_status()
1501 	val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);  in bnx2x_hw_enable_status()
1504 	val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);  in bnx2x_hw_enable_status()
1507 	val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);  in bnx2x_hw_enable_status()
1510 	val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);  in bnx2x_hw_enable_status()
1513 	val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);  in bnx2x_hw_enable_status()
1516 	val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);  in bnx2x_hw_enable_status()
1569 	u32 val = REG_RD(bp, addr);  in bnx2x_hc_int_enable()
1637 	val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_igu_int_enable()
1757 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_trylock_hw_lock()
2021 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_acquire_hw_lock()
2032 		lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_acquire_hw_lock()
2069 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_release_hw_lock()
2083 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_get_gpio()
2084 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_get_gpio()
2097 	gpio_reg = REG_RD(bp, MISC_REG_GPIO);  in bnx2x_get_gpio()
2111 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_set_gpio()
2112 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_set_gpio()
2125 	gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);  in bnx2x_set_gpio()
2173 	gpio_reg = REG_RD(bp, MISC_REG_GPIO);  in bnx2x_set_mult_gpio()
2214 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_set_gpio_int()
2215 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_set_gpio_int()
2228 	gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);  in bnx2x_set_gpio_int()
2271 	spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);  in bnx2x_set_spio()
3746 	SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));  in bnx2x_update_mfw_dump()
3967 		val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);  in bnx2x_acquire_alr()
4030 	aeu_mask = REG_RD(bp, aeu_addr);  in bnx2x_attn_int_asserted()
4050 			nig_mask = REG_RD(bp, nig_int_mask_addr);  in bnx2x_attn_int_asserted()
4123 				igu_acked = REG_RD(bp,  in bnx2x_attn_int_asserted()
4173 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
4192 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
4208 		val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);  in bnx2x_attn_int_deasserted1()
4223 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted1()
4239 		val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);  in bnx2x_attn_int_deasserted2()
4247 		val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);  in bnx2x_attn_int_deasserted2()
4254 			val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);  in bnx2x_attn_int_deasserted2()
4267 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted2()
4367 					REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);  in bnx2x_attn_int_deasserted3()
4372 					REG_RD(bp, MISC_REG_GRC_RSV_ATTN);  in bnx2x_attn_int_deasserted3()
4412 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_reset_global()
4426 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_clear_reset_global()
4438 	u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_reset_is_global()
4455 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_reset_done()
4475 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_reset_in_progress()
4489 	u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_reset_is_done()
4511 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_pf_load()
4549 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_clear_pf_load()
4580 	u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_get_load_status()
4594 	pr_cont(" [0x%08x] ", REG_RD(bp, reg));  in _print_parity()
5030 	attn.sig[0] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5033 	attn.sig[1] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5036 	attn.sig[2] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5039 	attn.sig[3] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5045 	attn.sig[3] &= ((REG_RD(bp,  in bnx2x_chk_parity_attn()
5052 		attn.sig[4] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5064 		val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);  in bnx2x_attn_int_deasserted4()
5088 		val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);  in bnx2x_attn_int_deasserted4()
5142 	attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5143 	attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5144 	attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5145 	attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5148 		      REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5198 	aeu_mask = REG_RD(bp, reg_addr);  in bnx2x_attn_int_deasserted()
6074 			   REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);  in bnx2x_init_def_sb()
6082 			bp->attn_group[index].sig[4] = REG_RD(bp,  in bnx2x_init_def_sb()
6566 		REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &  in bnx2x_post_irq_nic_init()
6737 		val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
6791 	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
6801 	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
6807 		REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);  in bnx2x_int_mem_test()
6808 	val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);  in bnx2x_int_mem_test()
6976 	val = REG_RD(bp, MISC_REG_SPIO_INT);  in bnx2x_setup_fan_failure_detection()
6981 	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);  in bnx2x_setup_fan_failure_detection()
6988 	u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_pf_disable()
7123 	val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);  in bnx2x_init_hw_common()
7128 	val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);  in bnx2x_init_hw_common()
7245 			val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);  in bnx2x_init_hw_common()
7477 	REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);  in bnx2x_init_hw_common()
7489 		SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));  in bnx2x_init_hw_common()
7666 	       REG_RD(bp, reg) &  in bnx2x_init_hw_port()
7671 	       REG_RD(bp, reg) &  in bnx2x_init_hw_port()
7726 	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);  in bnx2x_init_hw_port()
7730 		val = REG_RD(bp, reg_addr);  in bnx2x_init_hw_port()
7789 	while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)  in bnx2x_igu_clear_sb_gen()
7792 	if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {  in bnx2x_igu_clear_sb_gen()
7854 		vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :  in bnx2x_reset_nic_mode()
7859 			mac_en[i] = REG_RD(bp, port ?  in bnx2x_reset_nic_mode()
7976 		val = REG_RD(bp, addr);  in bnx2x_init_hw_func()
8233 		val = REG_RD(bp, main_mem_prty_clr);  in bnx2x_init_hw_func()
8248 		REG_RD(bp, main_mem_prty_clr);  in bnx2x_init_hw_func()
9036 			if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))  in bnx2x_reset_func()
9085 	val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);  in bnx2x_reset_port()
9514 		val = REG_RD(bp, addr);  in bnx2x_disable_close_the_gate()
9518 		val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);  in bnx2x_disable_close_the_gate()
9541 		val = REG_RD(bp, HC_REG_CONFIG_1);  in bnx2x_set_234_gates()
9546 		val = REG_RD(bp, HC_REG_CONFIG_0);  in bnx2x_set_234_gates()
9552 		val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);  in bnx2x_set_234_gates()
9608 	shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_reset_mcp_prep()
9644 		bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_init_shmem()
9808 		pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);  in bnx2x_er_poll_igu_vq()
9834 		sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);  in bnx2x_process_kill()
9835 		blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);  in bnx2x_process_kill()
9836 		port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);  in bnx2x_process_kill()
9837 		port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);  in bnx2x_process_kill()
9838 		pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);  in bnx2x_process_kill()
9840 			tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);  in bnx2x_process_kill()
10418 	vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);  in bnx2x_prev_unload_close_umac()
10434 	reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);  in bnx2x_prev_unload_close_mac()
10437 		val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);  in bnx2x_prev_unload_close_mac()
10453 			wb_data[0] = REG_RD(bp, base_addr + offset);  in bnx2x_prev_unload_close_mac()
10454 			wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);  in bnx2x_prev_unload_close_mac()
10464 		vals->emac_val = REG_RD(bp, vals->emac_addr);  in bnx2x_prev_unload_close_mac()
10471 			val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);  in bnx2x_prev_unload_close_mac()
10477 			vals->xmac_val = REG_RD(bp, vals->xmac_addr);  in bnx2x_prev_unload_close_mac()
10508 	if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &  in bnx2x_prev_is_after_undi()
10512 	if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {  in bnx2x_prev_is_after_undi()
10530 	tmp_reg = REG_RD(bp, addr);  in bnx2x_prev_unload_undi_inc()
10772 	reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);  in bnx2x_prev_unload_common()
10793 			REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);  in bnx2x_prev_unload_common()
10800 		tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);  in bnx2x_prev_unload_common()
10804 			tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);  in bnx2x_prev_unload_common()
10868 	hw_lock_val = REG_RD(bp, hw_lock_reg);  in bnx2x_prev_unload()
10881 	if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {  in bnx2x_prev_unload()
10942 	val = REG_RD(bp, MISC_REG_CHIP_NUM);  in bnx2x_get_common_hwinfo()
10944 	val = REG_RD(bp, MISC_REG_CHIP_REV);  in bnx2x_get_common_hwinfo()
10950 	val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);  in bnx2x_get_common_hwinfo()
10952 	val = REG_RD(bp, MISC_REG_BOND_ID);  in bnx2x_get_common_hwinfo()
10957 	if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {  in bnx2x_get_common_hwinfo()
10971 		val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);  in bnx2x_get_common_hwinfo()
10973 			val = REG_RD(bp, MISC_REG_PORT4MODE_EN);  in bnx2x_get_common_hwinfo()
10995 	val = (REG_RD(bp, 0x2874) & 0x55);  in bnx2x_get_common_hwinfo()
11002 	val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);  in bnx2x_get_common_hwinfo()
11010 	bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?  in bnx2x_get_common_hwinfo()
11019 		REG_RD(bp, bp->common.shmem2_base +  in bnx2x_get_common_hwinfo()
11147 		val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);  in bnx2x_get_igu_cam_info()
11226 		bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);  in bnx2x_link_settings_supported()
11230 			bp->port.phy_addr = REG_RD(  in bnx2x_link_settings_supported()
11234 			bp->port.phy_addr = REG_RD(  in bnx2x_link_settings_supported()
11931 	if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {  in bnx2x_get_hwinfo()
11953 		val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);  in bnx2x_get_hwinfo()
11964 			while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {  in bnx2x_get_hwinfo()
11969 			if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {  in bnx2x_get_hwinfo()
15103 	REG_RD(bp, pretend_reg);  in bnx2x_pretend_func()
15122 		val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :  in bnx2x_ptp_task()
15133 		timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :  in bnx2x_ptp_task()
15136 		timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :  in bnx2x_ptp_task()
15165 	timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :  in bnx2x_set_rx_ts()
15168 	timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :  in bnx2x_set_rx_ts()