Lines Matching refs:bnx2_write_phy
544 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) in bnx2_write_phy() function
1113 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); in bnx2_5709s_linkup()
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_5709s_linkup()
1387 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_bmsr1()
1396 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_bmsr1()
1413 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_test_and_enable_2g5()
1418 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_enable_2g5()
1423 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_test_and_enable_2g5()
1439 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_test_and_disable_2g5()
1444 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_disable_2g5()
1449 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_test_and_disable_2g5()
1467 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_forced_2g5()
1473 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); in bnx2_enable_forced_2g5()
1476 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_forced_2g5()
1496 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_enable_forced_2g5()
1511 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_forced_2g5()
1515 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); in bnx2_disable_forced_2g5()
1518 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_forced_2g5()
1535 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_disable_forced_2g5()
1543 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); in bnx2_5706s_force_link_dn()
1546 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); in bnx2_5706s_force_link_dn()
1548 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); in bnx2_5706s_force_link_dn()
1582 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_set_link()
1619 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_set_link()
1641 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); in bnx2_reset_phy()
1809 bnx2_write_phy(bp, bp->mii_adv, adv & in bnx2_setup_serdes_phy()
1812 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | in bnx2_setup_serdes_phy()
1817 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1820 bnx2_write_phy(bp, bp->mii_adv, adv); in bnx2_setup_serdes_phy()
1821 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1843 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_serdes_phy()
1849 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_serdes_phy()
1850 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | in bnx2_setup_serdes_phy()
2102 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2103 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000); in bnx2_setup_copper_phy()
2104 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | in bnx2_setup_copper_phy()
2119 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2136 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_copper_phy()
2145 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_copper_phy()
2192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); in bnx2_init_5709s_phy()
2193 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); in bnx2_init_5709s_phy()
2195 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_init_5709s_phy()
2199 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); in bnx2_init_5709s_phy()
2204 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); in bnx2_init_5709s_phy()
2206 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_init_5709s_phy()
2212 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); in bnx2_init_5709s_phy()
2214 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); in bnx2_init_5709s_phy()
2217 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); in bnx2_init_5709s_phy()
2219 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); in bnx2_init_5709s_phy()
2223 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); in bnx2_init_5709s_phy()
2225 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_init_5709s_phy()
2240 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); in bnx2_init_5708s_phy()
2241 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); in bnx2_init_5708s_phy()
2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); in bnx2_init_5708s_phy()
2246 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); in bnx2_init_5708s_phy()
2250 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); in bnx2_init_5708s_phy()
2255 bnx2_write_phy(bp, BCM5708S_UP1, val); in bnx2_init_5708s_phy()
2262 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2266 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); in bnx2_init_5708s_phy()
2267 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); in bnx2_init_5708s_phy()
2278 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2280 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); in bnx2_init_5708s_phy()
2281 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2303 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2305 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); in bnx2_init_5706s_phy()
2307 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2309 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); in bnx2_init_5706s_phy()
2314 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2316 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_5706s_phy()
2318 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2320 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); in bnx2_init_5706s_phy()
2335 bnx2_write_phy(bp, 0x18, 0x0c00); in bnx2_init_copper_phy()
2336 bnx2_write_phy(bp, 0x17, 0x000a); in bnx2_init_copper_phy()
2337 bnx2_write_phy(bp, 0x15, 0x310b); in bnx2_init_copper_phy()
2338 bnx2_write_phy(bp, 0x17, 0x201f); in bnx2_init_copper_phy()
2339 bnx2_write_phy(bp, 0x15, 0x9506); in bnx2_init_copper_phy()
2340 bnx2_write_phy(bp, 0x17, 0x401f); in bnx2_init_copper_phy()
2341 bnx2_write_phy(bp, 0x15, 0x14e2); in bnx2_init_copper_phy()
2342 bnx2_write_phy(bp, 0x18, 0x0400); in bnx2_init_copper_phy()
2346 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, in bnx2_init_copper_phy()
2350 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); in bnx2_init_copper_phy()
2355 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2357 bnx2_write_phy(bp, 0x18, val | 0x4000); in bnx2_init_copper_phy()
2360 bnx2_write_phy(bp, 0x10, val | 0x1); in bnx2_init_copper_phy()
2363 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2365 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_copper_phy()
2368 bnx2_write_phy(bp, 0x10, val & ~0x1); in bnx2_init_copper_phy()
2372 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL); in bnx2_init_copper_phy()
2380 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val); in bnx2_init_copper_phy()
2453 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | in bnx2_set_phy_loopback()
6061 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); in bnx2_5706_serdes_has_link()
6067 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_5706_serdes_has_link()
6074 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); in bnx2_5706_serdes_has_link()
6104 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6113 bnx2_write_phy(bp, 0x17, 0x0f01); in bnx2_5706_serdes_timer()
6120 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6130 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_5706_serdes_timer()
7178 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_nway_reset()
7192 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); in bnx2_nway_reset()
7896 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); in bnx2_ioctl()