Lines Matching refs:BIT
121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
123 #define AX_FC_ANEG BIT(2)
126 #define AX_CAP_COMP BIT(0)
153 #define PSR_DEV_READY BIT(7)
155 #define PSR_RESET_CLR BIT(15)
158 #define FER_IPALM BIT(0)
159 #define FER_DCRC BIT(1)
160 #define FER_RH3M BIT(2)
161 #define FER_HEADERSWAP BIT(7)
162 #define FER_WSWAP BIT(8)
163 #define FER_BSWAP BIT(9)
164 #define FER_INTHI BIT(10)
166 #define FER_IRQ_PULL BIT(11)
167 #define FER_RXEN BIT(14)
168 #define FER_TXEN BIT(15)
170 #define ISR_RXPKT BIT(0)
171 #define ISR_MDQ BIT(4)
172 #define ISR_TXT BIT(5)
173 #define ISR_TXPAGES BIT(6)
174 #define ISR_TXERR BIT(8)
175 #define ISR_LINK BIT(9)
177 #define IMR_RXPKT BIT(0)
178 #define IMR_MDQ BIT(4)
179 #define IMR_TXT BIT(5)
180 #define IMR_TXPAGES BIT(6)
181 #define IMR_TXERR BIT(8)
182 #define IMR_LINK BIT(9)
186 #define WFCR_PMEIND BIT(0) /* PME indication */
187 #define WFCR_PMETYPE BIT(1) /* PME I/O type */
188 #define WFCR_PMEPOL BIT(2) /* PME polarity */
189 #define WFCR_PMERST BIT(3) /* Reset PME */
190 #define WFCR_SLEEP BIT(4) /* Enable sleep mode */
191 #define WFCR_WAKEUP BIT(5) /* Enable wakeup mode */
192 #define WFCR_WAITEVENT BIT(6) /* Reserved */
193 #define WFCR_CLRWAKE BIT(7) /* Clear wakeup */
194 #define WFCR_LINKCH BIT(8) /* Enable link change */
195 #define WFCR_MAGICP BIT(9) /* Enable magic packet */
196 #define WFCR_WAKEF BIT(10) /* Enable wakeup frame */
197 #define WFCR_PMEEN BIT(11) /* Enable PME pin */
198 #define WFCR_LINKCHS BIT(12) /* Link change status */
199 #define WFCR_MAGICPS BIT(13) /* Magic packet status */
200 #define WFCR_WAKEFS BIT(14) /* Wakeup frame status */
201 #define WFCR_PMES BIT(15) /* PME pin status */
205 #define PSCR_PS_D1 BIT(0)
206 #define PSCR_PS_D2 BIT(1)
207 #define PSCR_FPS BIT(3) /* Enable fiber mode PS */
208 #define PSCR_SWPS BIT(4) /* Enable software */
210 #define PSCR_WOLPS BIT(5) /* Enable WOL PS */
211 #define PSCR_SWWOL BIT(6) /* Enable software select */
213 #define PSCR_PHYOSC BIT(7) /* Internal PHY OSC control */
214 #define PSCR_FOFEF BIT(8) /* Force PHY generate FEF */
215 #define PSCR_FOF BIT(9) /* Force PHY in fiber mode */
216 #define PSCR_PHYPD BIT(10) /* PHY power down. */
218 #define PSCR_PHYRST BIT(11) /* PHY reset signal. */
220 #define PSCR_PHYCSIL BIT(12) /* PHY cable energy detect */
221 #define PSCR_PHYCOFF BIT(13) /* PHY cable off */
222 #define PSCR_PHYLINK BIT(14) /* PHY link status */
223 #define PSCR_EEPOK BIT(15) /* EEPROM load complete */
225 #define MACCR_RXEN BIT(0) /* Enable RX */
226 #define MACCR_DUPLEX_FULL BIT(1) /* 1: Full, 0: Half */
227 #define MACCR_SPEED_100 BIT(2) /* 1: 100Mbps, 0: 10Mbps */
228 #define MACCR_RXFC_ENABLE BIT(3)
230 #define MACCR_TXFC_ENABLE BIT(4)
232 #define MACCR_PSI BIT(6) /* Software Cable-Off */
234 #define MACCR_PF BIT(7)
237 #define MACCR_PMM_RESET BIT(8)
252 #define TFBFCR_FREE_PAGE_LATCH BIT(6)
254 #define TFBFCR_TX_PAGE_SET BIT(13)
255 #define TFBFCR_MANU_ENTX BIT(15)
260 #define TXNR_TXB_ERR BIT(5)
261 #define TXNR_TXB_IDLE BIT(6)
263 #define TXNR_TXB_REINIT BIT(14)
264 #define TSNR_TXB_START BIT(15)
267 #define RXBCR1_RXB_DISCARD BIT(14)
268 #define RXBCR1_RXB_START BIT(15)
272 #define RXBCR2_RXB_READY BIT(13)
273 #define RXBCR2_RXB_IDLE BIT(14)
274 #define RXBCR2_RXB_REINIT BIT(15)
277 #define RTWCR_RX_LATCH BIT(15)
282 #define RPPER_RXEN BIT(0)
289 #define RXBSPCR_STUF_ENABLE BIT(15)
291 #define MCR_SBP BIT(8)
292 #define MCR_SM BIT(9)
293 #define MCR_CRCENLAN BIT(11)
294 #define MCR_STP BIT(12)
298 #define PCR_POLL_EN BIT(0)
299 #define PCR_POLL_FLOWCTRL BIT(1)
300 #define PCR_POLL_BMCR BIT(2)
307 #define MDIOCR_VALID BIT(13)
308 #define MDIOCR_READ BIT(14)
309 #define MDIOCR_WRITE BIT(15)
311 #define LCR_LED0_EN BIT(0)
312 #define LCR_LED0_100MODE BIT(1)
313 #define LCR_LED0_DUPLEX BIT(2)
314 #define LCR_LED0_LINK BIT(3)
315 #define LCR_LED0_ACT BIT(4)
316 #define LCR_LED0_COL BIT(5)
317 #define LCR_LED0_10MODE BIT(6)
318 #define LCR_LED0_DUPCOL BIT(7)
319 #define LCR_LED1_EN BIT(8)
320 #define LCR_LED1_100MODE BIT(9)
321 #define LCR_LED1_DUPLEX BIT(10)
322 #define LCR_LED1_LINK BIT(11)
323 #define LCR_LED1_ACT BIT(12)
324 #define LCR_LED1_COL BIT(13)
325 #define LCR_LED1_10MODE BIT(14)
326 #define LCR_LED1_DUPCOL BIT(15)
329 #define LCR_LED2_EN BIT(0)
330 #define LCR_LED2_100MODE BIT(1)
331 #define LCR_LED2_DUPLEX BIT(2)
332 #define LCR_LED2_LINK BIT(3)
333 #define LCR_LED2_ACT BIT(4)
334 #define LCR_LED2_COL BIT(5)
335 #define LCR_LED2_10MODE BIT(6)
336 #define LCR_LED2_DUPCOL BIT(7)
341 #define RXCR_PRO BIT(0)
342 #define RXCR_AMALL BIT(1)
343 #define RXCR_SEP BIT(2)
344 #define RXCR_AB BIT(3)
345 #define RXCR_AM BIT(4)
346 #define RXCR_AP BIT(5)
347 #define RXCR_ARP BIT(6)
371 #define EECR_READ_ACT BIT(8)
372 #define EECR_WRITE_ACT BIT(9)
373 #define EECR_WRITE_DISABLE BIT(10)
374 #define EECR_WRITE_ENABLE BIT(11)
375 #define EECR_EE_READY BIT(13)
376 #define EECR_RELOAD BIT(14)
377 #define EECR_RESET BIT(15)
380 #define TPCR_RAND_PKT_EN BIT(14)
381 #define TPCR_FIXED_PKT_EN BIT(15)
385 #define SPICR_RCEN BIT(0)
386 #define SPICR_QCEN BIT(1)
387 #define SPICR_RBRE BIT(3)
388 #define SPICR_PMM BIT(4)
389 #define SPICR_LOOPBACK BIT(8)
390 #define SPICR_CORE_RES_CLR BIT(10)
391 #define SPICR_SPI_RES_CLR BIT(11)
395 #define COERCR0_RXIPCE BIT(0)
396 #define COERCR0_RXIPVE BIT(1)
397 #define COERCR0_RXV6PE BIT(2)
398 #define COERCR0_RXTCPE BIT(3)
399 #define COERCR0_RXUDPE BIT(4)
400 #define COERCR0_RXICMP BIT(5)
401 #define COERCR0_RXIGMP BIT(6)
402 #define COERCR0_RXICV6 BIT(7)
404 #define COERCR0_RXTCPV6 BIT(8)
405 #define COERCR0_RXUDPV6 BIT(9)
406 #define COERCR0_RXICMV6 BIT(10)
407 #define COERCR0_RXIGMV6 BIT(11)
408 #define COERCR0_RXICV6V6 BIT(12)
414 #define COERCR1_IPCEDP BIT(0)
415 #define COERCR1_IPVEDP BIT(1)
416 #define COERCR1_V6VEDP BIT(2)
417 #define COERCR1_TCPEDP BIT(3)
418 #define COERCR1_UDPEDP BIT(4)
419 #define COERCR1_ICMPDP BIT(5)
420 #define COERCR1_IGMPDP BIT(6)
421 #define COERCR1_ICV6DP BIT(7)
422 #define COERCR1_RX64TE BIT(8)
423 #define COERCR1_RXPPPE BIT(9)
424 #define COERCR1_TCP6DP BIT(10)
425 #define COERCR1_UDP6DP BIT(11)
426 #define COERCR1_IC6DP BIT(12)
427 #define COERCR1_IG6DP BIT(13)
428 #define COERCR1_ICV66DP BIT(14)
429 #define COERCR1_RPCE BIT(15)
434 #define COETCR0_TXIP BIT(0)
435 #define COETCR0_TXTCP BIT(1)
436 #define COETCR0_TXUDP BIT(2)
437 #define COETCR0_TXICMP BIT(3)
438 #define COETCR0_TXIGMP BIT(4)
439 #define COETCR0_TXICV6 BIT(5)
440 #define COETCR0_TXTCPV6 BIT(8)
441 #define COETCR0_TXUDPV6 BIT(9)
442 #define COETCR0_TXICMV6 BIT(10)
443 #define COETCR0_TXIGMV6 BIT(11)
444 #define COETCR0_TXICV6V6 BIT(12)
450 #define COETCR1_TX64TE BIT(0)
451 #define COETCR1_TXPPPE BIT(1)
475 #define WFCR03_F0_EN BIT(0)
476 #define WFCR03_F1_EN BIT(4)
477 #define WFCR03_F2_EN BIT(8)
478 #define WFCR03_F3_EN BIT(12)
480 #define WFCR47_F4_EN BIT(0)
481 #define WFCR47_F5_EN BIT(4)
482 #define WFCR47_F6_EN BIT(8)
483 #define WFCR47_F7_EN BIT(12)