Lines Matching refs:pdata
63 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); in xgene_enet_ring_wr32() local
65 iowrite32(data, pdata->ring_csr_addr + offset); in xgene_enet_ring_wr32()
71 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); in xgene_enet_ring_rd32() local
73 *data = ioread32(pdata->ring_csr_addr + offset); in xgene_enet_ring_rd32()
78 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); in xgene_enet_write_ring_state() local
82 for (i = 0; i < pdata->ring_ops->num_ring_config; i++) { in xgene_enet_write_ring_state()
223 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_csr() argument
226 void __iomem *addr = pdata->eth_csr_addr + offset; in xgene_enet_wr_csr()
231 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata, in xgene_enet_wr_ring_if() argument
234 void __iomem *addr = pdata->eth_ring_if_addr + offset; in xgene_enet_wr_ring_if()
239 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_diag_csr() argument
242 void __iomem *addr = pdata->eth_diag_csr_addr + offset; in xgene_enet_wr_diag_csr()
247 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_mcx_csr() argument
250 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; in xgene_enet_wr_mcx_csr()
255 void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr, u32 wr_data) in xgene_enet_wr_mac() argument
258 struct net_device *ndev = pdata->ndev; in xgene_enet_wr_mac()
262 if (pdata->mdio_driver && ndev->phydev && in xgene_enet_wr_mac()
263 phy_interface_mode_is_rgmii(pdata->phy_mode)) { in xgene_enet_wr_mac()
269 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; in xgene_enet_wr_mac()
270 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET; in xgene_enet_wr_mac()
271 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; in xgene_enet_wr_mac()
272 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; in xgene_enet_wr_mac()
274 spin_lock(&pdata->mac_lock); in xgene_enet_wr_mac()
287 spin_unlock(&pdata->mac_lock); in xgene_enet_wr_mac()
290 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_csr() argument
293 void __iomem *addr = pdata->eth_csr_addr + offset; in xgene_enet_rd_csr()
298 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_diag_csr() argument
301 void __iomem *addr = pdata->eth_diag_csr_addr + offset; in xgene_enet_rd_diag_csr()
306 static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_mcx_csr() argument
309 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; in xgene_enet_rd_mcx_csr()
314 u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr) in xgene_enet_rd_mac() argument
317 struct net_device *ndev = pdata->ndev; in xgene_enet_rd_mac()
321 if (pdata->mdio_driver && ndev->phydev && in xgene_enet_rd_mac()
322 phy_interface_mode_is_rgmii(pdata->phy_mode)) { in xgene_enet_rd_mac()
328 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; in xgene_enet_rd_mac()
329 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET; in xgene_enet_rd_mac()
330 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; in xgene_enet_rd_mac()
331 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; in xgene_enet_rd_mac()
333 spin_lock(&pdata->mac_lock); in xgene_enet_rd_mac()
345 spin_unlock(&pdata->mac_lock); in xgene_enet_rd_mac()
350 u32 xgene_enet_rd_stat(struct xgene_enet_pdata *pdata, u32 rd_addr) in xgene_enet_rd_stat() argument
356 addr = pdata->mcx_stats_addr + STAT_ADDR_REG_OFFSET; in xgene_enet_rd_stat()
357 rd = pdata->mcx_stats_addr + STAT_READ_REG_OFFSET; in xgene_enet_rd_stat()
358 cmd = pdata->mcx_stats_addr + STAT_COMMAND_REG_OFFSET; in xgene_enet_rd_stat()
359 cmd_done = pdata->mcx_stats_addr + STAT_COMMAND_DONE_REG_OFFSET; in xgene_enet_rd_stat()
361 spin_lock(&pdata->stats_lock); in xgene_enet_rd_stat()
369 netdev_err(pdata->ndev, "mac stats read failed, addr: %04x\n", in xgene_enet_rd_stat()
374 spin_unlock(&pdata->stats_lock); in xgene_enet_rd_stat()
379 static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata) in xgene_gmac_set_mac_addr() argument
381 const u8 *dev_addr = pdata->ndev->dev_addr; in xgene_gmac_set_mac_addr()
388 xgene_enet_wr_mac(pdata, STATION_ADDR0_ADDR, addr0); in xgene_gmac_set_mac_addr()
389 xgene_enet_wr_mac(pdata, STATION_ADDR1_ADDR, addr1); in xgene_gmac_set_mac_addr()
392 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata) in xgene_enet_ecc_init() argument
394 struct net_device *ndev = pdata->ndev; in xgene_enet_ecc_init()
398 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); in xgene_enet_ecc_init()
401 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data); in xgene_enet_ecc_init()
412 static void xgene_gmac_reset(struct xgene_enet_pdata *pdata) in xgene_gmac_reset() argument
414 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1); in xgene_gmac_reset()
415 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, 0); in xgene_gmac_reset()
418 static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata) in xgene_enet_configure_clock() argument
420 struct device *dev = &pdata->pdev->dev; in xgene_enet_configure_clock()
423 struct clk *parent = clk_get_parent(pdata->clk); in xgene_enet_configure_clock()
425 switch (pdata->phy_speed) { in xgene_enet_configure_clock()
439 switch (pdata->phy_speed) { in xgene_enet_configure_clock()
457 static void xgene_gmac_set_speed(struct xgene_enet_pdata *pdata) in xgene_gmac_set_speed() argument
462 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0); in xgene_gmac_set_speed()
463 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2); in xgene_gmac_set_speed()
464 mc2 = xgene_enet_rd_mac(pdata, MAC_CONFIG_2_ADDR); in xgene_gmac_set_speed()
465 intf_ctl = xgene_enet_rd_mac(pdata, INTERFACE_CONTROL_ADDR); in xgene_gmac_set_speed()
466 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii); in xgene_gmac_set_speed()
468 switch (pdata->phy_speed) { in xgene_gmac_set_speed()
490 CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay); in xgene_gmac_set_speed()
491 CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay); in xgene_gmac_set_speed()
494 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value); in xgene_gmac_set_speed()
496 xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value); in xgene_gmac_set_speed()
501 xgene_enet_wr_mac(pdata, MAC_CONFIG_2_ADDR, mc2); in xgene_gmac_set_speed()
502 xgene_enet_wr_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl); in xgene_gmac_set_speed()
503 xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii); in xgene_gmac_set_speed()
504 xgene_enet_configure_clock(pdata); in xgene_gmac_set_speed()
506 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0); in xgene_gmac_set_speed()
507 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2); in xgene_gmac_set_speed()
510 static void xgene_enet_set_frame_size(struct xgene_enet_pdata *pdata, int size) in xgene_enet_set_frame_size() argument
512 xgene_enet_wr_mac(pdata, MAX_FRAME_LEN_ADDR, size); in xgene_enet_set_frame_size()
515 static void xgene_gmac_enable_tx_pause(struct xgene_enet_pdata *pdata, in xgene_gmac_enable_tx_pause() argument
520 xgene_enet_rd_mcx_csr(pdata, CSR_ECM_CFG_0_ADDR, &data); in xgene_gmac_enable_tx_pause()
527 xgene_enet_wr_mcx_csr(pdata, CSR_ECM_CFG_0_ADDR, data); in xgene_gmac_enable_tx_pause()
530 static void xgene_gmac_flowctl_tx(struct xgene_enet_pdata *pdata, bool enable) in xgene_gmac_flowctl_tx() argument
534 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); in xgene_gmac_flowctl_tx()
541 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data); in xgene_gmac_flowctl_tx()
543 pdata->mac_ops->enable_tx_pause(pdata, enable); in xgene_gmac_flowctl_tx()
546 static void xgene_gmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable) in xgene_gmac_flowctl_rx() argument
550 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); in xgene_gmac_flowctl_rx()
557 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data); in xgene_gmac_flowctl_rx()
560 static void xgene_gmac_init(struct xgene_enet_pdata *pdata) in xgene_gmac_init() argument
564 if (!pdata->mdio_driver) in xgene_gmac_init()
565 xgene_gmac_reset(pdata); in xgene_gmac_init()
567 xgene_gmac_set_speed(pdata); in xgene_gmac_init()
568 xgene_gmac_set_mac_addr(pdata); in xgene_gmac_init()
571 value = xgene_enet_rd_mac(pdata, MII_MGMT_CONFIG_ADDR); in xgene_gmac_init()
573 xgene_enet_wr_mac(pdata, MII_MGMT_CONFIG_ADDR, value); in xgene_gmac_init()
576 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value); in xgene_gmac_init()
578 xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value); in xgene_gmac_init()
581 xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0); in xgene_gmac_init()
584 xgene_enet_rd_mcx_csr(pdata, CSR_MULTI_DPF0_ADDR, &value); in xgene_gmac_init()
586 xgene_enet_wr_mcx_csr(pdata, CSR_MULTI_DPF0_ADDR, value); in xgene_gmac_init()
588 xgene_enet_wr_csr(pdata, RXBUF_PAUSE_THRESH, DEF_PAUSE_THRES); in xgene_gmac_init()
589 xgene_enet_wr_csr(pdata, RXBUF_PAUSE_OFF_THRESH, DEF_PAUSE_OFF_THRES); in xgene_gmac_init()
591 xgene_gmac_flowctl_tx(pdata, pdata->tx_pause); in xgene_gmac_init()
592 xgene_gmac_flowctl_rx(pdata, pdata->rx_pause); in xgene_gmac_init()
595 xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0); in xgene_gmac_init()
597 xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value); in xgene_gmac_init()
601 xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value); in xgene_gmac_init()
603 xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX); in xgene_gmac_init()
606 static void xgene_gmac_get_drop_cnt(struct xgene_enet_pdata *pdata, in xgene_gmac_get_drop_cnt() argument
611 xgene_enet_rd_mcx_csr(pdata, ICM_ECM_DROP_COUNT_REG0_ADDR, &count); in xgene_gmac_get_drop_cnt()
615 xgene_enet_rd_mcx_csr(pdata, ECM_CONFIG0_REG_0_ADDR, &count); in xgene_gmac_get_drop_cnt()
618 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata) in xgene_enet_config_ring_if_assoc() argument
622 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
623 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
624 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
625 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
628 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata, in xgene_enet_cle_bypass() argument
638 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb); in xgene_enet_cle_bypass()
642 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb); in xgene_enet_cle_bypass()
644 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb); in xgene_enet_cle_bypass()
648 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb); in xgene_enet_cle_bypass()
651 static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata) in xgene_gmac_rx_enable() argument
655 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); in xgene_gmac_rx_enable()
656 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN); in xgene_gmac_rx_enable()
659 static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata) in xgene_gmac_tx_enable() argument
663 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); in xgene_gmac_tx_enable()
664 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN); in xgene_gmac_tx_enable()
667 static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata) in xgene_gmac_rx_disable() argument
671 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); in xgene_gmac_rx_disable()
672 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN); in xgene_gmac_rx_disable()
675 static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata) in xgene_gmac_tx_disable() argument
679 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); in xgene_gmac_tx_disable()
680 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN); in xgene_gmac_tx_disable()
694 static int xgene_enet_reset(struct xgene_enet_pdata *pdata) in xgene_enet_reset() argument
696 struct device *dev = &pdata->pdev->dev; in xgene_enet_reset()
698 if (!xgene_ring_mgr_init(pdata)) in xgene_enet_reset()
701 if (pdata->mdio_driver) { in xgene_enet_reset()
702 xgene_enet_config_ring_if_assoc(pdata); in xgene_enet_reset()
707 clk_prepare_enable(pdata->clk); in xgene_enet_reset()
709 clk_disable_unprepare(pdata->clk); in xgene_enet_reset()
711 clk_prepare_enable(pdata->clk); in xgene_enet_reset()
717 status = acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev), in xgene_enet_reset()
720 acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev), in xgene_enet_reset()
726 xgene_enet_ecc_init(pdata); in xgene_enet_reset()
727 xgene_enet_config_ring_if_assoc(pdata); in xgene_enet_reset()
732 static void xgene_enet_clear(struct xgene_enet_pdata *pdata, in xgene_enet_clear() argument
745 xgene_enet_wr_ring_if(pdata, addr, data); in xgene_enet_clear()
748 static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata) in xgene_gport_shutdown() argument
750 struct device *dev = &pdata->pdev->dev; in xgene_gport_shutdown()
753 if (!IS_ERR(pdata->clk)) in xgene_gport_shutdown()
754 clk_disable_unprepare(pdata->clk); in xgene_gport_shutdown()
760 struct xgene_enet_pdata *pdata = netdev_priv(ndev); in xgene_enet_flowctrl_cfg() local
766 if (!phydev->duplex || !pdata->pause_autoneg) in xgene_enet_flowctrl_cfg()
769 if (pdata->tx_pause) in xgene_enet_flowctrl_cfg()
772 if (pdata->rx_pause) in xgene_enet_flowctrl_cfg()
787 if (tx_pause != pdata->tx_pause) { in xgene_enet_flowctrl_cfg()
788 pdata->tx_pause = tx_pause; in xgene_enet_flowctrl_cfg()
789 pdata->mac_ops->flowctl_tx(pdata, pdata->tx_pause); in xgene_enet_flowctrl_cfg()
792 if (rx_pause != pdata->rx_pause) { in xgene_enet_flowctrl_cfg()
793 pdata->rx_pause = rx_pause; in xgene_enet_flowctrl_cfg()
794 pdata->mac_ops->flowctl_rx(pdata, pdata->rx_pause); in xgene_enet_flowctrl_cfg()
802 struct xgene_enet_pdata *pdata = netdev_priv(ndev); in xgene_enet_adjust_link() local
803 const struct xgene_mac_ops *mac_ops = pdata->mac_ops; in xgene_enet_adjust_link()
807 if (pdata->phy_speed != phydev->speed) { in xgene_enet_adjust_link()
808 pdata->phy_speed = phydev->speed; in xgene_enet_adjust_link()
809 mac_ops->set_speed(pdata); in xgene_enet_adjust_link()
810 mac_ops->rx_enable(pdata); in xgene_enet_adjust_link()
811 mac_ops->tx_enable(pdata); in xgene_enet_adjust_link()
817 mac_ops->rx_disable(pdata); in xgene_enet_adjust_link()
818 mac_ops->tx_disable(pdata); in xgene_enet_adjust_link()
819 pdata->phy_speed = SPEED_UNKNOWN; in xgene_enet_adjust_link()
845 struct xgene_enet_pdata *pdata = netdev_priv(ndev); in xgene_enet_phy_connect() local
848 struct device *dev = &pdata->pdev->dev; in xgene_enet_phy_connect()
856 0, pdata->phy_mode); in xgene_enet_phy_connect()
876 pdata->phy_mode)) { in xgene_enet_phy_connect()
885 pdata->phy_speed = SPEED_UNKNOWN; in xgene_enet_phy_connect()
894 static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata, in xgene_mdiobus_register() argument
897 struct device *dev = &pdata->pdev->dev; in xgene_mdiobus_register()
898 struct net_device *ndev = pdata->ndev; in xgene_mdiobus_register()
943 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata) in xgene_enet_mdio_config() argument
945 struct net_device *ndev = pdata->ndev; in xgene_enet_mdio_config()
959 mdio_bus->priv = (void __force *)pdata->mcx_mac_addr; in xgene_enet_mdio_config()
960 mdio_bus->parent = &pdata->pdev->dev; in xgene_enet_mdio_config()
962 ret = xgene_mdiobus_register(pdata, mdio_bus); in xgene_enet_mdio_config()
968 pdata->mdio_bus = mdio_bus; in xgene_enet_mdio_config()
972 xgene_enet_mdio_remove(pdata); in xgene_enet_mdio_config()
977 void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata) in xgene_enet_phy_disconnect() argument
979 struct net_device *ndev = pdata->ndev; in xgene_enet_phy_disconnect()
985 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata) in xgene_enet_mdio_remove() argument
987 struct net_device *ndev = pdata->ndev; in xgene_enet_mdio_remove()
992 mdiobus_unregister(pdata->mdio_bus); in xgene_enet_mdio_remove()
993 mdiobus_free(pdata->mdio_bus); in xgene_enet_mdio_remove()
994 pdata->mdio_bus = NULL; in xgene_enet_mdio_remove()