756 	writel(csr, &adapter->regs->rxdma.csr);  in et131x_rx_dma_enable()
758 	csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_enable()
761 		csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_enable()
775 	       &adapter->regs->rxdma.csr);  in et131x_rx_dma_disable()
776 	csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_disable()
779 		csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_disable()
1538 	struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;  in et131x_config_rx_dma_regs()
2117 		writel(0, &adapter->regs->rxdma.max_pkt_time);  in et131x_set_rx_dma_timer()
2118 		writel(1, &adapter->regs->rxdma.num_pkt_done);  in et131x_set_rx_dma_timer()
2126 	struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;  in nic_return_rfd()
2231 	writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);  in nic_rx_pkts()
2919 	regs_buff[num++] = readl(&aregs->rxdma.csr);  in et131x_get_regs()
2920 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);  in et131x_get_regs()
2921 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);  in et131x_get_regs()
2922 	regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);  in et131x_get_regs()
2923 	regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);  in et131x_get_regs()
2924 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);  in et131x_get_regs()
2925 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);  in et131x_get_regs()
2926 	regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);  in et131x_get_regs()
2927 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);  in et131x_get_regs()
2928 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);  in et131x_get_regs()
2929 	regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);  in et131x_get_regs()
2930 	regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);  in et131x_get_regs()
2931 	regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);  in et131x_get_regs()
2932 	regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);  in et131x_get_regs()
2933 	regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);  in et131x_get_regs()
2934 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);  in et131x_get_regs()
2935 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);  in et131x_get_regs()
2936 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);  in et131x_get_regs()
2937 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);  in et131x_get_regs()
2938 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);  in et131x_get_regs()
2939 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);  in et131x_get_regs()
2940 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);  in et131x_get_regs()
2941 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);  in et131x_get_regs()
2942 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);  in et131x_get_regs()
2943 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);  in et131x_get_regs()
2944 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);  in et131x_get_regs()
2945 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);  in et131x_get_regs()
2946 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);  in et131x_get_regs()
2947 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);  in et131x_get_regs()