Lines Matching defs:sdhci_host
368 struct sdhci_host { struct
370 const char *hw_name; /* Hardware bus name */
372 unsigned int quirks; /* Deviations from spec. */
437 unsigned int quirks2; /* More deviations from spec. */
484 int irq; /* Device IRQ */
485 void __iomem *ioaddr; /* Mapped address */
486 phys_addr_t mapbase; /* physical address base */
487 char *bounce_buffer; /* For packing SDMA reads/writes */
488 dma_addr_t bounce_addr;
489 unsigned int bounce_buffer_size;
491 const struct sdhci_ops *ops; /* Low level hw interface */
494 struct mmc_host *mmc; /* MMC structure */
495 struct mmc_host_ops mmc_host_ops; /* MMC host ops */
496 u64 dma_mask; /* custom DMA mask */
499 struct led_classdev led; /* LED control */
500 char led_name[32];
503 spinlock_t lock; /* Mutex */
505 int flags; /* Host attributes */
520 unsigned int version; /* SDHCI spec. version */
522 unsigned int max_clk; /* Max possible freq (MHz) */
523 unsigned int timeout_clk; /* Timeout freq (KHz) */
524 u8 max_timeout_count; /* Vendor specific max timeout count */
525 unsigned int clk_mul; /* Clock Muliplier value */
527 unsigned int clock; /* Current clock (MHz) */
528 u8 pwr; /* Current voltage */
529 u8 drv_type; /* Current UHS-I driver type */
530 bool reinit_uhs; /* Force UHS-related re-initialization */
532 bool runtime_suspended; /* Host is runtime suspended */
533 bool bus_on; /* Bus power prevents runtime suspend */
534 bool preset_enabled; /* Preset is enabled */
535 bool pending_reset; /* Cmd/data reset is pending */
536 bool irq_wake_enabled; /* IRQ wakeup is enabled */
537 bool v4_mode; /* Host Version 4 Enable */
538 bool use_external_dma; /* Host selects to use external DMA */
539 bool always_defer_done; /* Always defer to complete requests */
541 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
542 struct mmc_command *cmd; /* Current command */
543 struct mmc_command *data_cmd; /* Current data command */
544 struct mmc_command *deferred_cmd; /* Deferred command */
545 struct mmc_data *data; /* Current data request */
546 unsigned int data_early:1; /* Data finished before cmd */
548 struct sg_mapping_iter sg_miter; /* SG state for PIO */
549 unsigned int blocks; /* remaining PIO blocks */
551 int sg_count; /* Mapped sg entries */
552 int max_adma; /* Max. length in ADMA descriptor */
554 void *adma_table; /* ADMA descriptor table */
555 void *align_buffer; /* Bounce buffer */
557 size_t adma_table_sz; /* ADMA descriptor table size */
558 size_t align_buffer_sz; /* Bounce buffer size */
560 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
561 dma_addr_t align_addr; /* Mapped bounce buffer */
563 unsigned int desc_sz; /* ADMA current descriptor size */
564 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
566 struct workqueue_struct *complete_wq; /* Request completion wq */
567 struct work_struct complete_work; /* Request completion work */
569 struct timer_list timer; /* Timer for timeouts */
570 struct timer_list data_timer; /* Timer for data timeouts */
573 struct dma_chan *rx_chan;
574 struct dma_chan *tx_chan;
577 u32 caps; /* CAPABILITY_0 */
578 u32 caps1; /* CAPABILITY_1 */
579 bool read_caps; /* Capability flags have been read */
581 bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */
582 unsigned int ocr_avail_sdio; /* OCR bit masks */
583 unsigned int ocr_avail_sd;
584 unsigned int ocr_avail_mmc;
585 u32 ocr_mask; /* available voltages */
587 unsigned timing; /* Current timing */
589 u32 thread_isr;
592 u32 ier;
594 bool cqe_on; /* CQE is operating */
595 u32 cqe_ier; /* CQE interrupt mask */
596 u32 cqe_err_ier; /* CQE error interrupt mask */
598 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
599 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
624 u32 (*read_l)(struct sdhci_host *host, int reg); argument