Lines Matching refs:MSDC_CFG
55 #define MSDC_CFG 0x0 macro
657 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
658 readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
792 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
795 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
850 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
868 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
875 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
877 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
899 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
902 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
921 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
925 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
929 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
934 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
935 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
1053 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1689 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
2854 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
2882 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()